CDCM6208V2G
- Superior Performance with Low Power:
- Low Noise Synthesizer (265 fs-rms Typical
Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms
Typical Jitter) - 0.5 W Typical Power Consumption
- High Channel-to-Channel Isolation and
Excellent PSRR - Device Performance Customizable Through
Flexible 1.8 V, 2.5 V and 3.3 V Power
Supplies, Allowing Mixed Output Voltages
- Low Noise Synthesizer (265 fs-rms Typical
- Flexible Frequency Planning:
- 4x Integer Down-divided Differential Clock
Outputs Supporting LVPECL-like, CML, or
LVDS-like Signaling - 4x Fractional or Integer Divided Differential
Clock Outputs Supporting HCSL, LVDS-like
Signaling, or Eight CMOS Outputs - Fractional Output Divider Achieve 0 ppm to < 1
ppm Frequency Error and Eliminates need for
Crystal Oscillators and Other Clock Generators - Output frequencies up to 800 MHz
- 4x Integer Down-divided Differential Clock
- Two Differential Inputs, XTAL Support, Ability for
Smart Switching - SPI, I2C™, and Pin Programmable
- Professional user GUI for Quick Design
Turnaround - 7 × 7 mm 48-QFN package (RGZ)
- –40 °C to 85 °C temperature range
The CDCM6208V2G is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V2G also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V2G can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.
In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k – 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k – 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency.
In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k – 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V2G is packaged in a small 48-pin 7 mm × 7 mm QFN package.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers datasheet | PDF | HTML | 2016/3/7 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
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