產品詳細資料

Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1800 Coprocessors 2 Dual Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100/1000, 2-Port 1Gb switch PCIe 1 PCIe Gen 2 Hardware accelerators 1 Image Subsystem Processor, 1 Image Video Accelerator, 2 Viterbi Decoder, Audio Tracking Features Multimedia Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1800 Coprocessors 2 Dual Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100/1000, 2-Port 1Gb switch PCIe 1 PCIe Gen 2 Hardware accelerators 1 Image Subsystem Processor, 1 Image Video Accelerator, 2 Viterbi Decoder, Audio Tracking Features Multimedia Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
FCCSP (ACD) 784 529 mm² 23 x 23
  • Architecture Designed for Infotainment Applications
  • Video, Image, and Graphics Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
  • Dual Arm® Cortex®-A15 Microprocessor Subsystem
  • Up to Two C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible with C67x and C64x+
    • Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 2.5MB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB Supported per EMIF
  • Dual ARM® Cortex®-M4 Image Processing Units (IPU)
  • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA Subsystem
  • Display Subsystem
    • Display Controller with DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • Video Processing Engine (VPE)
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante® GC320 Core
  • Dual-Core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) Modules
    • Support for up to Eight Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Five Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • SATA Interface
  • Media Local Bus (MLB) Subsystem
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • Three High-Speed USB 2.0 Dual-Role Devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 Subsystems with Two 5-Gbps Lanes
    • One 2-Lane Gen2-Compliant Port
    • or Two 1-Lane Gen2-Compliant Ports
  • Up to Two Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • Modular Controller Area Network (MCAN) Module
    • CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
  • MIPI CSI-2 Camera Serial Interface
  • Up to 247 General-Purpose I/O (GPIO) Pins
  • Device Security Features
    • Hardware Crypto Accelerators and DMA
    • Firewalls
    • JTAG® Lock
    • Secure Keys
    • Secure ROM and Boot
    • Customer Programmable Keys and OTP Data
  • Power, Reset, and Clock Management
  • On-Chip Debug with CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 784-Pin BGA (ACD)
  • Architecture Designed for Infotainment Applications
  • Video, Image, and Graphics Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
  • Dual Arm® Cortex®-A15 Microprocessor Subsystem
  • Up to Two C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible with C67x and C64x+
    • Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 2.5MB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB Supported per EMIF
  • Dual ARM® Cortex®-M4 Image Processing Units (IPU)
  • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA Subsystem
  • Display Subsystem
    • Display Controller with DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • Video Processing Engine (VPE)
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante® GC320 Core
  • Dual-Core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) Modules
    • Support for up to Eight Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Five Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • SATA Interface
  • Media Local Bus (MLB) Subsystem
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • Three High-Speed USB 2.0 Dual-Role Devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 Subsystems with Two 5-Gbps Lanes
    • One 2-Lane Gen2-Compliant Port
    • or Two 1-Lane Gen2-Compliant Ports
  • Up to Two Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • Modular Controller Area Network (MCAN) Module
    • CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
  • MIPI CSI-2 Camera Serial Interface
  • Up to 247 General-Purpose I/O (GPIO) Pins
  • Device Security Features
    • Hardware Crypto Accelerators and DMA
    • Firewalls
    • JTAG® Lock
    • Secure Keys
    • Secure ROM and Boot
    • Customer Programmable Keys and OTP Data
  • Power, Reset, and Clock Management
  • On-Chip Debug with CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 784-Pin BGA (ACD)

DRA77xP and DRA76xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA77xP and DRA76xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA77x and DRA76x (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA77x and DRA76x Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA77xP and DRA76xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA77xP and DRA76xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA77x and DRA76x (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA77x and DRA76x Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 44
類型 標題 日期
* Data sheet DRA77xP, DRA76xP Infotainment Applications Processor Silicon Revision 1.0 datasheet (Rev. E) PDF | HTML 2018年 12月 10日
* Errata DRA7xx Silicon Errata (Rev. B) PDF | HTML 2024年 9月 8日
* User guide DRA77xP, DRA76xP, DRA75xP, DRA74xP Technical Reference Manual (Rev. D) PDF | HTML 2024年 5月 25日
Application note Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 2021年 5月 5日
More literature Building your application with security in mind (Rev. E) 2020年 10月 28日
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 2020年 8月 24日
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020年 1月 6日
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019年 6月 11日
Application note Achieving Early CAN Response on DRA7xx Devices 2018年 11月 28日
Application note DRA74x_75x/DRA72x Performance (Rev. A) 2018年 10月 31日
Application note Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 2018年 9月 14日
Application note The Implementation of YUV422 Output for SRV 2018年 8月 2日
Application note MMC DLL Tuning (Rev. B) 2018年 7月 31日
Application note Integrating AUTOSAR on TI SoC: Fundamentals 2018年 6月 18日
Application note ECC/EDC on TDAxx (Rev. B) 2018年 6月 13日
Application note Tools and Techniques to Root Case Failures in Video Capture Subsystem 2018年 6月 12日
Application note Sharing VPE Between VISIONSDK and PSDKLA 2018年 5月 4日
User guide LP87565C-Q1 and TPS65917-Q1 User’s Guide to Power DRA7xxP and TDA2Pxx (Rev. A) 2018年 4月 20日
Application note Android Boot Optimization on DRA7xx Devices (Rev. A) 2018年 2月 13日
Technical article Jacinto™ DRA automotive processors drive digital cockpit solutions PDF | HTML 2018年 1月 12日
Application note Flashing Utility - mflash 2018年 1月 9日
Application note Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 2017年 11月 30日
Application note Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 2017年 11月 27日
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017年 11月 7日
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017年 11月 3日
Application note Robust Rear-View Camera (RVC) App Report 2017年 9月 13日
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017年 9月 12日
Application note Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 2017年 8月 14日
Application note Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 2017年 7月 12日
White paper Revolutionize the automotive cockpit 2017年 6月 2日
Application note Linux Boot Time Optimizations on DRA7xx Devices 2017年 3月 31日
Application note Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 2017年 2月 17日
Application note Early Splash Screen on DRA7x Devices 2017年 1月 31日
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016年 12月 15日
Application note Gstreamer Migration Guidelines 2016年 4月 26日
User guide Jacinto6 Android Video Decoder Software Design Specification User's Guide 2016年 4月 21日
User guide Jacinto6 Android Video Encoder Software Design Specification User's Guide 2016年 4月 21日
Application note Flashing Binaries to DRA7xx Factory Boards Using DFU 2016年 4月 14日
Application note Tools and Techniques for Audio Debugging 2016年 4月 13日
Application note Debugging Tools and Techniques With IPC3.x 2016年 3月 30日
Application note Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 2016年 1月 15日
White paper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 2014年 10月 14日
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014年 8月 13日
White paper Today’s high-end infotainment soon becoming mainstream 2014年 6月 2日

設計與開發

電源供應解決方案

為 DRA76P 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

開發板

J6PEVM577P — DRA7xP 評估模組

The DRA77xP/DRA76xP-ACD is an evaluation platform designed to allow scalability and re-use across DRA77xP and DRA76xP JacintoTM Infotainment System-on-Chips (SoCs), it is based on Jacinto DRA77xP SoC that incorporates a heterogeneous, scalable architecture that includes a mix of two ARM Cortex-A15 (...)

使用指南: PDF
軟體開發套件 (SDK)

PROCESSOR-SDK-ANDROID-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
DRA710 適用於資訊娛樂系統與儀錶板,且含繪圖的 600 MHz ARM Cortex-A15 SoC 處理器 DRA712 適用車載資訊娛樂系統與儀錶板,且含圖形與雙 Arm Cortex-M4 的 600 MHz ARM Cortex-A15 SoC 處理器 DRA714 適用於資訊娛樂系統與儀錶板,且含繪圖和 DSP 的 600 MHz ARM Cortex-A15 SoC 處理器 DRA716 適用於資訊娛樂系統與儀錶板,且含繪圖和 DSP 的 800 MHz ARM Cortex-A15 SoC 處理器 DRA718 適用於資訊娛樂系統與儀錶板,且含繪圖和 DSP 的 1 GHz ARM Cortex-A15 SoC 處理器 DRA722 適用於車載資訊娛樂系統與儀錶板,且含圖形與 DSP 的 800MHz Arm Cortex-A15 SoC 處理器 DRA724 適用於車載資訊娛樂系統與儀錶板,且含圖形與 DSP 的 1GHz Arm Cortex-A15 SoC 處理器 DRA725 適用於車載資訊娛樂系統與儀錶板,且含圖形與 DSP 的 1.2GHz Arm Cortex-A15 SoC 處理器 DRA726 適用於車載資訊娛樂系統與儀錶板且具有圖形與 DSP 的 1.5 GHz Arm Cortex-A15 DRA74P 具有 ISP 並與 DRA74x SoC 處理器針腳相容的多核心 SoC 處理器 DRA75P 適用於資訊娛樂系統應用、具有 ISP 並與 DRA75x SoC 針腳相容的多核心 SoC 處理器 DRA76P 適用於數位駕駛艙應用並具有 ISP 的高效能多核心 SoC 處理器 DRA77P 適用於數位駕駛艙應用並具有延伸周邊設備和 ISP 的高效能多核心 SoC DRA790 適用於音訊放大器且具有 500 MHz C66x DSP 的 300 MHz ARM Cortex-A15 SoC 處理器 DRA791 適用於音訊放大器且具有 750 MHz C66x DSP 的 300 MHz ARM Cortex-A15 SoC 處理器 DRA793 適用於音訊放大器且具有 750 MHz C66x DSP 的 500 MHz ARM Cortex-A15 SoC 處理器 DRA797 適用於音訊放大器且具有 750 MHz C66x DSP 的 800 MHz ARM Cortex-A15 SoC 處理器
數位訊號處理器 (DSP)
DRA780 適用於音訊放大器且具有 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA781 適用於音訊放大器且具有 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA782 適用於音訊放大器且具有 2 個 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA783 適用於音訊放大器且具有 2 個 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA785 適用於音訊放大器且具有 2 個 1000 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA786 適用於音訊放大器且具有 2 個 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 和 EVE 的 SoC 處理器 DRA787 適用於音訊放大器且具有 2 個 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 和 EVE 的 SoC 處理器 DRA788 適用於音訊放大器,且具有 2 個 1000 MHz C66x DSP 和 1 個 EVE 及 2 個雙 Arm Cortex-M4 的 SoC 處理器
下載選項
軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
DRA710 適用於資訊娛樂系統與儀錶板,且含繪圖的 600 MHz ARM Cortex-A15 SoC 處理器 DRA712 適用車載資訊娛樂系統與儀錶板,且含圖形與雙 Arm Cortex-M4 的 600 MHz ARM Cortex-A15 SoC 處理器 DRA714 適用於資訊娛樂系統與儀錶板,且含繪圖和 DSP 的 600 MHz ARM Cortex-A15 SoC 處理器 DRA716 適用於資訊娛樂系統與儀錶板,且含繪圖和 DSP 的 800 MHz ARM Cortex-A15 SoC 處理器 DRA718 適用於資訊娛樂系統與儀錶板,且含繪圖和 DSP 的 1 GHz ARM Cortex-A15 SoC 處理器 DRA722 適用於車載資訊娛樂系統與儀錶板,且含圖形與 DSP 的 800MHz Arm Cortex-A15 SoC 處理器 DRA724 適用於車載資訊娛樂系統與儀錶板,且含圖形與 DSP 的 1GHz Arm Cortex-A15 SoC 處理器 DRA725 適用於車載資訊娛樂系統與儀錶板,且含圖形與 DSP 的 1.2GHz Arm Cortex-A15 SoC 處理器 DRA726 適用於車載資訊娛樂系統與儀錶板且具有圖形與 DSP 的 1.5 GHz Arm Cortex-A15 DRA746 具圖形與 DSP 且適用車載資訊娛樂系統與儀錶板的雙 1.5 GHz Arm Cortex-A15 SoC 處理器 DRA74P 具有 ISP 並與 DRA74x SoC 處理器針腳相容的多核心 SoC 處理器 DRA756 適用於車載資通訊系統的雙 1.5 GHz A15、雙 EVE、雙 DSP、延伸週邊設備 SoC 處理器 DRA75P 適用於資訊娛樂系統應用、具有 ISP 並與 DRA75x SoC 針腳相容的多核心 SoC 處理器 DRA76P 適用於數位駕駛艙應用並具有 ISP 的高效能多核心 SoC 處理器 DRA77P 適用於數位駕駛艙應用並具有延伸周邊設備和 ISP 的高效能多核心 SoC DRA790 適用於音訊放大器且具有 500 MHz C66x DSP 的 300 MHz ARM Cortex-A15 SoC 處理器 DRA791 適用於音訊放大器且具有 750 MHz C66x DSP 的 300 MHz ARM Cortex-A15 SoC 處理器 DRA793 適用於音訊放大器且具有 750 MHz C66x DSP 的 500 MHz ARM Cortex-A15 SoC 處理器 DRA797 適用於音訊放大器且具有 750 MHz C66x DSP 的 800 MHz ARM Cortex-A15 SoC 處理器
數位訊號處理器 (DSP)
DRA780 適用於音訊放大器且具有 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA781 適用於音訊放大器且具有 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA782 適用於音訊放大器且具有 2 個 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA783 適用於音訊放大器且具有 2 個 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA785 適用於音訊放大器且具有 2 個 1000 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA786 適用於音訊放大器且具有 2 個 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 和 EVE 的 SoC 處理器 DRA787 適用於音訊放大器且具有 2 個 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 和 EVE 的 SoC 處理器 DRA788 適用於音訊放大器,且具有 2 個 1000 MHz C66x DSP 和 1 個 EVE 及 2 個雙 Arm Cortex-M4 的 SoC 處理器
下載選項
軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
DRA710 適用於資訊娛樂系統與儀錶板,且含繪圖的 600 MHz ARM Cortex-A15 SoC 處理器 DRA712 適用車載資訊娛樂系統與儀錶板,且含圖形與雙 Arm Cortex-M4 的 600 MHz ARM Cortex-A15 SoC 處理器 DRA714 適用於資訊娛樂系統與儀錶板,且含繪圖和 DSP 的 600 MHz ARM Cortex-A15 SoC 處理器 DRA716 適用於資訊娛樂系統與儀錶板,且含繪圖和 DSP 的 800 MHz ARM Cortex-A15 SoC 處理器 DRA718 適用於資訊娛樂系統與儀錶板,且含繪圖和 DSP 的 1 GHz ARM Cortex-A15 SoC 處理器 DRA722 適用於車載資訊娛樂系統與儀錶板,且含圖形與 DSP 的 800MHz Arm Cortex-A15 SoC 處理器 DRA724 適用於車載資訊娛樂系統與儀錶板,且含圖形與 DSP 的 1GHz Arm Cortex-A15 SoC 處理器 DRA725 適用於車載資訊娛樂系統與儀錶板,且含圖形與 DSP 的 1.2GHz Arm Cortex-A15 SoC 處理器 DRA726 適用於車載資訊娛樂系統與儀錶板且具有圖形與 DSP 的 1.5 GHz Arm Cortex-A15 DRA74P 具有 ISP 並與 DRA74x SoC 處理器針腳相容的多核心 SoC 處理器 DRA75P 適用於資訊娛樂系統應用、具有 ISP 並與 DRA75x SoC 針腳相容的多核心 SoC 處理器 DRA76P 適用於數位駕駛艙應用並具有 ISP 的高效能多核心 SoC 處理器 DRA77P 適用於數位駕駛艙應用並具有延伸周邊設備和 ISP 的高效能多核心 SoC DRA790 適用於音訊放大器且具有 500 MHz C66x DSP 的 300 MHz ARM Cortex-A15 SoC 處理器 DRA791 適用於音訊放大器且具有 750 MHz C66x DSP 的 300 MHz ARM Cortex-A15 SoC 處理器 DRA793 適用於音訊放大器且具有 750 MHz C66x DSP 的 500 MHz ARM Cortex-A15 SoC 處理器 DRA797 適用於音訊放大器且具有 750 MHz C66x DSP 的 800 MHz ARM Cortex-A15 SoC 處理器
數位訊號處理器 (DSP)
DRA780 適用於音訊放大器且具有 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA781 適用於音訊放大器且具有 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA782 適用於音訊放大器且具有 2 個 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA783 適用於音訊放大器且具有 2 個 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA785 適用於音訊放大器且具有 2 個 1000 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA786 適用於音訊放大器且具有 2 個 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 和 EVE 的 SoC 處理器 DRA787 適用於音訊放大器且具有 2 個 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 和 EVE 的 SoC 處理器 DRA788 適用於音訊放大器,且具有 2 個 1000 MHz C66x DSP 和 1 個 EVE 及 2 個雙 Arm Cortex-M4 的 SoC 處理器
下載選項
IDE、配置、編譯器或偵錯程式

CCSTUDIO Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

支援產品和硬體

支援產品和硬體

此設計資源支援此類別中多數產品。

檢查產品詳細資料頁面以確認支援。

啟動 下載選項
作業系統 (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
支援軟體

VCTR-3P-MICROSAR — 適用於微控制器和高性能電腦 (HPC) 的 Vector MICROSAR AUTOSAR 軟體

MICROSAR 與 DaVinci 產品系列透過適用於微控制器與 HPC 的精密嵌入式軟體和強大開發工具,簡化 ECU 開發。有了先進的基礎架構軟體,您即可為 ECU 建立最佳基礎,並利用相關工具簡化所有相關開發作業。MICROSAR 嵌入式軟體是根據 AUTOSAR 經典和適應性等相關標準所開發。軟體也適合符合最高 ASIL D 之 ISO 26262 標準的安全相關應用。此外,智慧網路安全功能可保護控制單元免受未經授權的存取和竄改。Vector 涵蓋所有汽車與其他工業應用的使用案例。對於配備高性能電腦的軟體定義車輛 (SDV),其可提供現代車輛作業系統,以做為開放式模組化軟體生態系統。
模擬型號

DRA7xxP and TDA2Px BSDL Files

SPRM750.ZIP (34 KB) - BSDL Model
模擬型號

DRA7xxP and TDA2Px IBIS Files

SPRM748.ZIP (36622 KB) - IBIS Model
模擬型號

DRA7xxP and TDA2Px Thermal Model

SPRM749.ZIP (2 KB) - Thermal Model
計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
使用指南: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCCSP (ACD) 784 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片