DS25CP102

現行

具 TX 預強調和 Rx 等化功能的 3.125-Gbps 2x2 LVDS 交叉點交換器

產品詳細資料

Function Crosspoint, Equalizer Protocols CML, LVDS, LVPECL Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (MBits) 3125 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Crosspoint, Equalizer Protocols CML, LVDS, LVPECL Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (MBits) 3125 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (RGH) 16 16 mm² 4 x 4
  • DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation
  • Pin Configurable, Fully Differential, Non-Blocking Architecture
  • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter
  • Wide Input Common Mode Voltage Range Allows DC-Coupled Interface to CML and LVPECL Drivers
  • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, Minimizes Board Space
  • 8 kV ESD on LVDS I/O Pins Protects Adjoining Components
  • Small 4 mm x 4 mm WQFN-16 Space Saving Package

All trademarks are the property of their respective owners.

  • DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation
  • Pin Configurable, Fully Differential, Non-Blocking Architecture
  • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter
  • Wide Input Common Mode Voltage Range Allows DC-Coupled Interface to CML and LVPECL Drivers
  • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, Minimizes Board Space
  • 8 kV ESD on LVDS I/O Pins Protects Adjoining Components
  • Small 4 mm x 4 mm WQFN-16 Space Saving Package

All trademarks are the property of their respective owners.

The DS25CP102 is a 3.125 Gbps 2x2 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture allows connections of any input to any output or outputs.

The DS25CP102 features two levels (Off and On) of transmit pre-emphasis (PE) and two levels (Off and On) of receive equalization (EQ).

Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower device insertion and return losses, reduce component count and further minimize board space.

The DS25CP102 is a 3.125 Gbps 2x2 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture allows connections of any input to any output or outputs.

The DS25CP102 features two levels (Off and On) of transmit pre-emphasis (PE) and two levels (Off and On) of receive equalization (EQ).

Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower device insertion and return losses, reduce component count and further minimize board space.

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DS25CP102Q-Q1 現行 具有 TX 預強調和 RX 等化功能的自動 3.125-Gbps 2x2 LVDS 交叉點開關 Automotive qualified, temperature range (-40C to 85C)

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類型 標題 日期
* Data sheet 3.125 Gbps 2X2 LVDS Crosspoint sw w/ Xmit Pre-Emphasis & Receive Equalization datasheet (Rev. E) 2013年 3月 4日
Application note LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) 2013年 4月 29日
Application note AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A) 2013年 4月 26日
EVM User's guide 3.125 Gbps 2x2 LVDS Crosspoint Switch Evaluation Board 2012年 1月 25日

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開發板

DS25CP102EVK — 3.125 Gbps 2x2 LVDS 交叉點開關評估板

The DS25CP102EVK is an evaluation kit designed for demonstrating performance of the DS25CP102, a 3.125 Gbps 2x2 LVDS Crosspoint Switch with transmit pre-emphasis and receive equalization. The evaluation kit is comprised of the DS25CP102 with its associated input and output SMA connectors and (...)

使用指南: PDF
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模擬型號

DS25CP102 IBIS Model

SNLM064.ZIP (12 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
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