DS90C032QML
- Single Event Latchup (SEL) Immune 120 MeV-cm2/mg
- High Impedance LVDS Inputs with Power-Off.
- Accepts Small Swing (330 mV) Differential Signal Levels
- Low Power Dissipation
- Low Differential Skew
- Low Chip to Chip Skew
- Pin Compatible with DS26C32A
- Compatible with IEEE 1596.3 SCI LVDS Standard
All trademarks are the property of their respective owners.
The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications.
您可能會感興趣的類似產品
功能相同，但針腳輸出與所比較的裝置不同。
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS90C032QML LVDS Quad CMOS Differential Line Receiver datasheet (Rev. D) | 2013/4/12 | |||
| * | 輻射及可靠性報告 | DS90C032xLQMLV SEE Report | 2012/5/9 | |||
| * | 輻射及可靠性報告 | DS90C032xLQMLV TID Report | 2012/5/9 | |||
| * | SMD | DS90C032QML SMD 5962-95834 | 2016/6/21 | |||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018/8/3 | ||||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018/5/16 | ||||
| 應用說明 | AN-1110 LVDS Quad Dynamic I CC vs Frequency | 2004/5/15 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| LCCC (NAJ) | 20 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。