DS90CF384AQ-Q1
- Automotive Grade Device, AEC-Q100 Grade 3 Qualified
- Operating Temperature Range: –40°C to +85°C
- 20 to 65 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- Best–in–Class Set & Hold Times on RxOUTPUTs
- Rx Power Consumption <142 mW (typ) @65MHz Grayscale
- Rx Power-down Mode <200μW (max)
- ESD Rating >7 kV (HBM), >700V (EIAJ)
- Supports VGA, SVGA, XGA and Dual Pixel SXGA.
- PLL Requires No External Components
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 56-Lead TSSOP Package
All trademarks are the property of their respective owners.
The DS90CF384AQ receiver converts the four LVDS data streams at up to 1.8 Gbps throughput (227 Megabytes/sec bandwidth) back into parallel 28 bits of LVCMOS/LVTTL data. In a Display application, the 28 bits include: 24 bits of RGB data and up to 4 bits of video control (Hsync, Vsync, DE and CNTL).
The DS90CF384AQ device is enhanced over prior generation FPD-Link receivers, provides a wider data valid time on the receiver output and is offered as an AEC-Q100 grade 3 device.
FPD-Link is an ideal means to solve EMI and cable size problems associated with wide, high speed LVCMOS/LVTTL interfaces.
技術文件
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檢視所有 6 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz datasheet (Rev. A) | 2013年 4月 17日 | |
| Application note | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | 2018年 6月 29日 | ||
| Application note | AN-1032 An Introduction to FPD-Link (Rev. C) | 2017年 8月 8日 | ||
| Application note | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | 2004年 5月 15日 | ||
| Application note | AN-1056 STN Application Using FPD-Link | 2004年 5月 14日 | ||
| Application note | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | 2004年 5月 14日 |
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使用指南: PDF
| 封裝 | 引腳 | 下載 |
|---|---|---|
| TSSOP (DGG) | 56 | 檢視選項 |
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