DS90CR286AT-Q1
- 20 to 66 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- Best–in–Class Setup & Hold Times on
Rx Outputs - Rx Power Consumption < 270 mW (typ)
at 66 MHz Worst Case - Rx Power-down Mode < 200 μW (max)
- ESD Rating: 4 kV (HBM), 1 kV (CDM)
- PLL Requires No External Components
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 56-Pin DGG (TSSOP) Package
- Operating Temperature: −40°C to +105°C
- Automotive AEC-Q100 Grade 2 Qualified
The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output clock's rising edge.
The receiver LVDS clock operates at rates from 20 to 66 MHz. The DS90CR286AT-Q1 phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into 28-bit parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps.
The DS90CR286AT-Q1 device is enhanced over prior generation receivers due to a wider data valid time on the receiver output. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip OpenLDI-to-RGB bridge conversion. LVDS data transmission over cable interconnect is not recommended for this device.
Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1 receiver must ensure an acceptable skew margin budget (RSKM). Details regarding RSKM can be found in the Application Information section.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS90CR286AT-Q1 3.3 V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz datasheet (Rev. A) | PDF | HTML | 2015/12/6 | ||
| 應用說明 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/9 | ||||
| 應用說明 | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | 2016/1/13 |
設計與開發
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DS90CR285-86ATQEVM — DS90CR285 和 DS90CR286AT-Q1 通道連結 I SerDes 評估模組
FLINK3V8BT-85 — 適用於 FPD-Link 系列之串聯器和解串器 LVDS 產品的評估套件
The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。