DS90CR288A
- 20 to 85 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- 2.5 / 0 ns Set & Hold Times on TxINPUTs
- Low Power Consumption
- ±1V Common-Mode Range (around +1.2V)
- Narrow Bus Reduces Cable Size and Cost
- Up to 2.38 Gbps Throughput
- Up to 297.5 Mbytes/sec Bandwidth
- 345 mV (typ) Swing LVDS Devices for Low EMI
- PLL Requires no External Components
- Rising Edge Data Strobe
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 56-Lead TSSOP Package
The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.
The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet (Rev. G) | 2013/3/5 | |||
| 應用說明 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/9 | ||||
| 應用說明 | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | 2016/1/13 | |||
| 設計指南 | Channel Link I Design Guide | 2007/3/29 | ||||
| 應用說明 | Multi-Drop Channel-Link Operation | 2004/10/4 | ||||
| 應用說明 | CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications | 1998/10/5 |
設計與開發
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FLINK3V8BT-85 — 適用於 FPD-Link 系列之串聯器和解串器 LVDS 產品的評估套件
The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。