DS90LT012A
- Compatible with ANSI TIA/EIA-644-A Standard
- >400 Mbps (200 MHz) switching rates
- 100 ps differential skew (typical)
- 3.5 ns maximum propagation delay
- Integrated line termination resistor (102Ω typical)
- Single 3.3V power supply design (2.7V to 3.6V range)
- Power down high impedance on LVDS inputs
- Accepts small swing (350 mV typical) differential signal levels
- LVDS receiver inputs accept LVDS/BLVDS/LVPECL inputs
- Supports open, short and terminated input fail-safe
- Pinout simplifies PCB layout
- Low Power Dissipation (10mW typical@ 3.3V static)
- SOT-23 5-lead package
- Leadless WSON-8 package (3x3 mm body size)
- Electrically similar to the DS90LV018A
- Fabricated with advanced CMOS process technology
- Industrial temperature operating range (−40°C to +85°C)
The DS90LV012A and DS90LT012A are single CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Swing (LVDS) technology
The DS90LV012A and DS90LT012A accept low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receivers also support open, shorted, and terminated (100Ω) input fail-safe. The receiver output will be HIGH for all fail-safe conditions. The DS90LV012A has a pinout designed for easy PCB layout. The DS90LT012A includes an input line termination resistor for point-to-point applications.
The DS90LV012A and DS90LT012A, and companion LVDS line driver provide a new alternative to high power PECL/ECL devices for high speed interface applications.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS90LV012A / DS90LT012A 3-V LVDS Single CMOS Differential Line Receiver datasheet (Rev. E) | PDF | HTML | 2024/3/1 | ||
| 應用說明 | Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls | 2020/10/29 | ||||
| 應用說明 | Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners | 2019/6/29 | ||||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018/8/3 | ||||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018/5/16 | ||||
| 應用說明 | AN-1821 CPRI Repeater System (Rev. A) | 2013/4/26 | ||||
| 白皮書 | Eye Opening Enhancements extend the reach of high-speed Interfaces | 2002/10/1 | ||||
| 應用說明 | An Overview of LVDS Technology | 1998/10/5 |
設計與開發
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DS90LV047-48AEVM — DS90LV047-48AEVM 評估模組
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-23 (DBV) | 5 | Ultra Librarian |
訂購與品質
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