首頁 時鐘與計時 時鐘抖動清除器
首頁
時鐘與計時
時鐘抖動清除器

LMK04803

現行

具雙串接 PLL 和整合式 1.9 GHz VCO 的低雜訊時脈抖動清除器

立即訂購
產品規格表

LMK04803

現行
產品規格表 立即訂購

產品詳細資料

Number of input channels 2 Number of outputs 14 RMS jitter (fs) 111 Features 0 Delay Output frequency (min) (MHz) 0.22 Output frequency (max) (MHz) 2030 Output type LVCMOS, LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85
Number of input channels 2 Number of outputs 14 RMS jitter (fs) 111 Features 0 Delay Output frequency (min) (MHz) 0.22 Output frequency (max) (MHz) 2030 Output type LVCMOS, LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85
WQFN (NKD) 64 81 mm² (9 mm × 9 mm)
  • Ultra-Low RMS Jitter Performance
    • 111 fs RMS Jitter (12 kHz to 20 MHz)
    • 123 fs RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Integrated Low-Noise Crystal Oscillator
      Circuit
    • Holdover Mode when Input Clocks are Lost
    • Automatic or Manual Triggering/Recovery
  • PLL2
    • Normalized PLL Noise Floor of –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO
  • 2 Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50 % Duty Cycle Output Divides, 1 to 1045 (Even
    and Odd)
  • 12 LVPECL, LVDS, or LVCMOS Programmable
    Outputs
  • Digital Delay: Fixed or Dynamically Adjustable
  • 25 ps Step Analog Delay Control.
  • 14 Differential Outputs. Up to 26 Single Ended.
    • Up to 6 VCXO/Crystal Buffered Outputs
  • Clock Rates of up to 1536 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock
    Distribution
  • Industrial Temperature Range: –40 to 85°C
  • 3.15-V to 3.45-V Operation
  • 2 Dedicated Buffered/Divided OSCin Clocks
  • Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
  • Ultra-Low RMS Jitter Performance
    • 111 fs RMS Jitter (12 kHz to 20 MHz)
    • 123 fs RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Integrated Low-Noise Crystal Oscillator
      Circuit
    • Holdover Mode when Input Clocks are Lost
    • Automatic or Manual Triggering/Recovery
  • PLL2
    • Normalized PLL Noise Floor of –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO
  • 2 Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50 % Duty Cycle Output Divides, 1 to 1045 (Even
    and Odd)
  • 12 LVPECL, LVDS, or LVCMOS Programmable
    Outputs
  • Digital Delay: Fixed or Dynamically Adjustable
  • 25 ps Step Analog Delay Control.
  • 14 Differential Outputs. Up to 26 Single Ended.
    • Up to 6 VCXO/Crystal Buffered Outputs
  • Clock Rates of up to 1536 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock
    Distribution
  • Industrial Temperature Range: –40 to 85°C
  • 3.15-V to 3.45-V Operation
  • 2 Dedicated Buffered/Divided OSCin Clocks
  • Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)

The LMK0480x family is the industry’s highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.

The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

The LMK0480x family is the industry’s highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.

The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
filter 尋找其它 時鐘抖動清除器
下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
針腳對針腳的功能與所比較的裝置相同。
LMK04808 現行 具雙迴路 PLL 和整合式 2.9 GHz VCO 的低雜訊時脈抖動清除器 Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.9 GHz VCO
LMK04805 現行 具雙串接 PLL 和整合式 2.2 GHz VCO 的低雜訊時脈抖動清除器 Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO
LMK04806 現行 具雙串接 PLL 和整合式 2.5 GHz VCO 的低雜訊時脈抖動清除器 Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.5 GHz VCO
功能相似於所比較的產品。
LMK04821 現行 具 JESD204B 支援的超低抖動合成器與抖動清除器 LMK04821( it has additional features and better performance)

技術文件

找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 6
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet (Rev. K) PDF | HTML 2014/12/24
應用說明 Clocking for Medical Ultrasound Systems (Rev. A) PDF | HTML 2020/9/30
設計指南 TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide 2013/9/3
應用說明 Using the LMK0480x/LMK04906 for Hitless Switching and Holdover 2013/7/12
使用指南 TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) 2011/12/29
設計指南 Clock Conditioner Owner's Manual 2006/11/10

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TSW1265EVM — 寬頻雙路接收器參考設計和評估平台

The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL (...)

支援產品和硬體
有庫存
限制：
??asset.out-of-stock-ti_zh_TW??
無法提供
開發板

TSW3084EVM — 寬頻發射訊號鏈評估板和參考設計

The TSW3084EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution the TSW3084EVM includes (...)

使用指南: PDF
支援產品和硬體
有庫存
限制：
??asset.out-of-stock-ti_zh_TW??
無法提供
開發板

TSW30H84EVM — 寬頻發射訊號鏈評估板和參考設計

The TSW30H84EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (Please see LMK04800) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution (...)

使用指南: PDF
支援產品和硬體
有庫存
限制：
??asset.out-of-stock-ti_zh_TW??
無法提供
開發模組 (EVM) 的 GUI

SLAC507 — TSW308x EVM Software

支援產品和硬體
開發模組 (EVM) 的 GUI

SLAC532 — TSW4806 Installer GUI

支援產品和硬體
支援軟體

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM)：CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。

支援產品和硬體
模擬型號

LMK04803 IBIS Model (Rev. C)

SNAM097C.ZIP (111 KB) - IBIS 模型
支援產品和硬體
設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。

支援產品和硬體
設計工具

PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具

PLLATINUMSIM-SW 為一模擬工具，可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬，包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。

支援產品和硬體
參考設計

TIDA-00074 — 寬頻射頻轉數位複雜接收器 - 回饋訊號鏈

這是一款寬頻複合接收器參考設計和評估平台，非常適合作為發射器數位預失真的回饋接收器使用。EVM 訊號鏈非常適合高中頻 (IF) 複合回饋應用，其中包含一個複合解調器、TI 的 LMH6521 雙通道 DVGA 和 ADS5402 12 位元 800-MSPS 雙通道 ADC。透過修改板載濾波器元件，訊號鏈可針對各種頻率計劃進行配置。EVM 也包括 TI 的 LMK04808 雙 PLL 時鐘抖動清除器和產生器，用以提供板載低雜訊時脈解決方案。可透過 GUI 或透過具有 FPGA 的高速連接器控制 LMH6521 DVGA 增益。

支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
WQFN (NKD) 64 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片