LMK04828-EP
- EP Features
- Gold Bondwires
- Temperature Range: –55 to +105 °C
- Lead Finish SnPb
- Maximum Distribution Frequency: 3.2 GHz
- JESD204B Support
- Ultra-Low RMS Jitter
- 88-fs RMS Jitter (12 kHz to 20 MHz)
- 91-fs RMS Jitter (100 Hz to 20 MHz)
- –162.5 dBc/Hz Noise Floor at 245.76 MHz
- Up to 14 Differential
Device Clocks From PLL2
- Up to 7 SYSREF Clocks
- Maximum Clock Output Frequency 3.2 GHz
- LVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2
- Up to 1 Buffered VCXO/Crystal Output From
PLL1
- LVPECL, LVDS, 2xLVCMOS Programmable
- Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
- Dual Loop PLLatinum™ PLL Architecture
- PLL1
- Up to 3 Redundant Input
Clocks
- Automatic and Manual Switchover Modes
- Hitless Switching and LOS
- Integrated Low-Noise Crystal Oscillator Circuit
- Holdover Mode When Input Clocks are Lost
- Up to 3 Redundant Input
Clocks
- PLL2
- Normalized [1 Hz] PLL Noise Floor of
–227 dBc/Hz - Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Two Integrated Low-Noise VCOs
- Normalized [1 Hz] PLL Noise Floor of
- 50% Duty Cycle Output Divides, 1 to 32
(Even and Odd) - Precision Digital Delay, Dynamically Adjustable
- 25-ps Step Analog Delay
- 3.15-V to 3.45-V Operation
- Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)
The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support.
The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.
The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK04828-EP ideal for providing flexible high-performance clocking trees.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner datasheet | PDF | HTML | 2017/4/3 | ||
| 應用說明 | Multi-Clock Synchronization | 2019/12/30 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (NKD) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。