SN54HC138
- Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
- Wide Operating Voltage Range (2 V to 6 V)
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 80-µA Maximum ICC
- Typical tpd = 15 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1-µA Maximum
- Active Low Outputs ( Selected Output is Low)
- Incorporate Three Enable Inputs to Simplify Cascading or Data Reception
The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
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封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
CDIP (J) | 16 | Ultra Librarian |
CFP (W) | 16 | Ultra Librarian |
LCCC (FK) | 20 | Ultra Librarian |
訂購與品質
內含資訊:
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊:
- 晶圓廠位置
- 組裝地點