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LVDS、M-LVDS 和 PECL IC

SN65EPT21

現行

3.3-V ecl 差動接收器

立即訂購
產品規格表

SN65EPT21

現行
產品規格表 立即訂購

產品詳細資料

Function Receiver, Translator Protocols LVDS, PECL Number of transmitters 0 Number of receivers 1 Signaling rate (Mbps) 600 Input signal LVDS, PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver, Translator Protocols LVDS, PECL Number of transmitters 0 Number of receivers 1 Signaling rate (Mbps) 600 Input signal LVDS, PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) VSSOP (DGK) 8 14.7 mm² (3 mm × 4.9 mm)
  • 1 ns Propagation Delay
  • Fmax > 300MHz
  • Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
  • 24-mA TTL Output
  • Built-In Temperature Compensation
  • Drop-In Compatible to the MC10EPT21, MC100EPT21
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data
  • 1 ns Propagation Delay
  • Fmax > 300MHz
  • Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
  • 24-mA TTL Output
  • Built-In Temperature Compensation
  • Drop-In Compatible to the MC10EPT21, MC100EPT21
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data

The SN65EPT21 is a differential PECL-to-TTL translator. It operates on +3.3 V supply and ground only. The device includes circuitry to maintain inputs at Vcc/2 when left open.

The VBB pin is a reference voltage output for the device. When the device is used in single-ended mode, the unused input should be tied to VBB. This reference voltage can also be used to bias the input when it is ac coupled. When it is used, place a 0.01µF decoupling capacitor between VCC and VBB. Also limit the sink/source current to < 0.5 mA to VBB. Leave VBB open when it is not used.

The SN65EPT21 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.

The SN65EPT21 is a differential PECL-to-TTL translator. It operates on +3.3 V supply and ground only. The device includes circuitry to maintain inputs at Vcc/2 when left open.

The VBB pin is a reference voltage output for the device. When the device is used in single-ended mode, the unused input should be tied to VBB. This reference voltage can also be used to bias the input when it is ac coupled. When it is used, place a 0.01µF decoupling capacitor between VCC and VBB. Also limit the sink/source current to < 0.5 mA to VBB. Leave VBB open when it is not used.

The SN65EPT21 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 3.3V ECL Differential Receiver datasheet 2009/2/10
應用說明 AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 2007/10/17

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模擬型號

SN65EPT21 IBIS Model

SLLM145.ZIP (16 KB) - IBIS 模型
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian
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