現在提供此產品的更新版本
功能相同，但引腳輸出與所比較的裝置不同
SN65HVD257
- Meets the Requirements of ISO11898-2
- Turbo CAN:
- Short and Symmetrical Propagation Delay
Times and Fast Loop Times for Enhanced
Timing Margin - Higher Data Rates in CAN Networks
- Short and Symmetrical Propagation Delay
- I/O Voltage Range Supports 3.3-V and 5-V MCUs
- Ideal Passive Behavior When Unpowered
- Bus and Logic Pins are High Impedance (No
Load) - Power Up and Power Down With Glitch-Free
Operation on Bus
- Bus and Logic Pins are High Impedance (No
- Protection Features
- HBM ESD Protection Exceeds ±12 kV
- Bus Fault Protection –27 V to 40 V
- Undervoltage Protection on Supply Pins
- Driver Dominant Time Out (TXD DTO)
- SN65HVD257: Receiver-Dominant Time Out
(RXD DTO) - SN65HVD257: FAULT Output Pin
- Thermal Shutdown Protection
- Characterized for –40°C to 125°C Operation
This CAN transceiver meets the ISO1189-2 High Speed CAN (Controller Area Network) Physical Layer standard. It is designed for data rates in excess of 1 Mbps for CAN in short networks, and enhanced timing margin and higher data rates in long and highly-loaded networks. The device provides many protection features to enhance device and CAN-network robustness. The SN65HVD257 device adds additional features, allowing for easy design of redundant and multitopology networks with fault indication for higher levels of functional safety in the CAN system.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN65HVD25x Turbo CAN Transceivers for Higher Data Rates and Large Networks Including Features for Functional Safety datasheet (Rev. D) | PDF | HTML | 2015年 5月 9日 |
| Application note | CAN and LIN transceiver low-power modes | 2019年 2月 25日 | ||
| EVM User's guide | SN65HVD257 CAN EVM | 2012年 8月 16日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
SN65HVD257EVM — SN65HVD257 CAN 評估模組
The Texas Instruments SN65HVD257 CAN EVM helps designers evaluate the operation and performance of the SN65HVD257 CAN transceiver. The SN65HVD257 includes many features for functional safety network implementation such as redundant CAN networks. The SN65HVD257 CAN EVM also provides PCB footprints (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
TINA-TI — 基於 SPICE 的類比模擬程式
TIDA-00629 — IEC 61000 ESD、EFT 及突波防護 CAN 參考設計
TIDA-00061 — 冗餘 CAN 參考設計
This reference design demonstrates how to implement redundant (parallel) CAN for functional safety at the physical layer. It includes two SN65HVD257 CAN transceivers and additional logic to ensure both transceivers are receiving the same data.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。