SN65LVDS100
- Designed for Signaling Rates ≥ 2 Gbps
- Total Jitter < 65 ps
- Low-Power Alternative for the MC100EP16
- Low 100-ps (Maximum) Part-to-Part Skew
- 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Input Voltage Range - Inputs Electrically Compatible With LVPECL,
CML, and LVDS Signal Levels - 3.3-V Supply Operation
- LVDT Integrates 110-Ω Terminating Resistor
- Offered in SOIC and MSOP
The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.
The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance.
The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is not used, it should be unconnected or open.
All devices are characterized for operation from –40°C to 85°C.
您可能會感興趣的類似產品
功能相似於所比較的產品。
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN65LVDx10x Differential Translator/Repeater datasheet (Rev. E) | PDF | HTML | 2015/7/20 | ||
| Application brief | How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver | 2019/1/9 | ||||
| 應用說明 | Signaling Rate vs. Distance for Differential Buffers | 2010/1/26 | ||||
| 應用說明 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007/10/17 | ||||
| 應用說明 | DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML | 2003/2/19 | ||||
| 更多文件說明 | HPL EVM Program | 2002/8/29 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
SN65CML100EVM — SN65CML100 評估模組
The EVM allows evaluation of operation of theSN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters. Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can beobserved across on board terminations, or via direct connection to 50-ohm (...)
SN65LVDS100EVM — SN65LVDS100 評估模組
The EVM allows evaluation of operation of the SN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters. Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can be observed across on board terminations, or via direct connection to (...)
PMP9767 — 適用於 12 位元 500 MSPS ADC 的免 LDO 電源參考設計
資料轉換器的電氣性能取決於其供應電壓的清潔度。一般使用線性穩壓器 (LDO)，但其具有低效率與高功率損耗，不適合可攜式應用。
改用 TPS62231 和 TPS62237 等切換模式電源供應器 (SMPS)，是符合成本效益且有效率的電源供應器解決方案。這種解決方案不會降低 12 位元 ADS540x 系列類比轉數位轉換器 (ADC) 的性能，且不會浪費過多電源。測試報告顯示兩個電源供應器之間的訊號雜訊比 (SNR) 和無雜散動態範圍 (SFDR) 比較，展示相同的性能。
TIDA-00074 — 寬頻射頻轉數位複雜接收器 - 回饋訊號鏈
這是一款寬頻複合接收器參考設計和評估平台，非常適合作為發射器數位預失真的回饋接收器使用。EVM 訊號鏈非常適合高中頻 (IF) 複合回饋應用，其中包含一個複合解調器、TI 的 LMH6521 雙通道 DVGA 和 ADS5402 12 位元 800-MSPS 雙通道 ADC。透過修改板載濾波器元件，訊號鏈可針對各種頻率計劃進行配置。EVM 也包括 TI 的 LMK04808 雙 PLL 時鐘抖動清除器和產生器，用以提供板載低雜訊時脈解決方案。可透過 GUI 或透過具有 FPGA 的高速連接器控制 LMH6521 DVGA 增益。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。