SN65LVDS250
- Greater Than 2.0 Gbps Operation
- Nonblocking Architecture Allows Each Output to be Connected to Any Input
- Pk.Pk Jitter:
- 60 ps Typical at 2.0 Gbps
- 110 ps Typical at 2.5 Gbps
- Compatible With ANSI TIA/EIA-644-A LVDS Standard
- Available Packaging 38-Pin TSSOP
- 25 mV of Input Voltage Threshold Hysteresis
- Propagation Delay Times: 800 ps Typical
- Inputs Electrically Compatible With LVPECL, CML and LVDS Signal Levels
- Operates From a Single 3.3-V Supply
- Low Power: 110 mA Typical
- Integrated 110-
Line Termination Resistors Available With SN65LVDT250 - APPLICATIONS
- Clock Buffering/Clock Muxing
- Wireless Base Stations
- High-Speed Network Routing
- Telecom/Datacom
The SN65LVDS250 and SN65LVDT250 are 4x4 nonblocking crosspoint switches in a flow-through pin-out allowing for ease in PCB layout. Low-voltage differential signaling (LVDS) is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT250 incorporates 110- termination resistors for those applications where board space is a premium.
The SN65LVDS250 and SN65LVDT250 are characterized for operation from –40°C to 85°C.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN65LVDS250, SN65LVDT250: LVDS 4X4 Crosspoint Switch datasheet (Rev. B) | 2004/10/14 |
設計與開發
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SN65LVDS125AEVM — SN65LVDS125 評估模組
The SN65LVDS125A is a 4 x 4 non-blocking cross point switch. Low-Voltage differential signaling (LVDS) is used to achieve signaling rates of 1.5 Gbps per channel. Each output driver includes a 4:1 multiplexer to allow any input to be routed to any output.Internal signal paths are fully differential (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (DBT) | 38 | Ultra Librarian |
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建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。