SN65LVDS93
- 28:4 Data Channel Compression at up to 1.904 Gigabits per Second Throughput
- Suited for Point-to-Point Subsystem Communication With Very Low EMI
- 28 Data Channels Plus Clock in Low-Voltage TTL and 4 Data Channels Plus Clock Out Low-Voltage Differential
- Selectable Rising or Falling Clock Edge Triggered Inputs
- Bus Pins Tolerate 6-kV HBM ESD
- Operates From a Single 3.3-V Supply and 250 mW (Typ)
- 5-V Tolerant Data Inputs
- Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
- Consumes <1 mW When Disabled
- Wide Phase-Lock Input Frequency Range 20 MHz to 68 MHz
- No External Components Required for PLL
- Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
- Industrial Temperature Qualified TA = -40°C to 85°C
- Replacement for the DS90CR285
The SN65LVDS93 LVDS serdes (serializer/ deserializer) transmitter contains four 7-bit parallel- load serial-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input and the possible use of the shutdown/clear (SHTDN). SHTDN is an active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers at a low level.
The SN65LVDS93 is characterized for operation over ambient air temperatures of -40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LVDS Serdes Transmitter datasheet (Rev. G) | 2009/5/19 | |||
| 應用說明 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/9 | ||||
| 應用說明 | AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) | 2018/8/3 | ||||
| Application brief | LVDS Serdes 48 EVM Kit Setup And Usage | 1998/12/17 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
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