SN65LVDS94
- 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput
- Suited for Point-to-Point Subsystem Communication With Very Low EMI
- 4 Data Channels and Clock Low-Voltage Differential Channels in and 28 Data and Clock Out Low-Voltage TTL Channels Out
- Operates From a Single 3.3-V Supply and 250 mW (Typ)
- 5-V Tolerant SHTDN\ Input
- Rising Clock Edge Triggered Outputs
- Bus Pins Tolerate 4-kV HBM ESD
- Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
- Consumes <1 mW When Disabled
- Wide Phase-Lock Input Frequency Range
- 20 MHz to 65 MHz
- No External Components Required for PLL
- Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard
- Industrial Temperature Qualified TA = -40°C to 85°C
- Replacement for the DS90CR286
The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).
The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN\) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.
The SN65LVDS94 is characterized for operation over ambient air temperatures of -40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LVDS Serdes Receiver datasheet (Rev. F) | 2006/1/27 | |||
| 應用說明 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/9 | ||||
| Application brief | LVDS Serdes 48 EVM Kit Setup And Usage | 1998/12/17 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。