SN74AS286
- Generate Either Odd or Even Parity forNine Data Lines
- Cascadable for n-Bit Parity
- Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port
- Glitch-Free Bus During Power Up/Down
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
The SN54AS286 and SN74AS286 universal 9-bit parity
generators/checkers feature a local output for parity checking and a
48-mA bus-driving
parity input/output (I/O) port for parity generation/checking. The
word-length capability is easily expanded by cascading.
The transmit (
) control input
is implemented specifically to accommodate cascading. When is low, the parity tree is
disabled and PARITY ERROR remains at a high logic level regardless of
the input levels. When is
high, the parity tree is enabled. PARITY ERROR indicates a parity
error when either an even number of inputs (A-I) are high and PARITY
I/O is forced to a low logic level, or when an odd number of inputs
are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches.
The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 9-Bit Parity Generators/Checker With Bus-Driver Parity I/O Port datasheet (Rev. B) | 1994年 12月 1日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
| Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
| Application note | Advanced Schottky Load Management | 1997年 2月 1日 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||
| Application note | Live Insertion | 1996年 10月 1日 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 1995年 8月 1日 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點