產品詳細資料

Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Ron (typ) (Ω) 5 CON (typ) (pF) 2.5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Powered-off protection Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Ron (typ) (Ω) 5 CON (typ) (pF) 2.5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Powered-off protection Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
SOIC (D) 14 51.9 mm² 8.65 x 6 SSOP (DBQ) 16 29.4 mm² 4.9 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5
  • Standard 126-type pinout
  • 5-Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • Standard 126-type pinout
  • 5-Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, Class II

The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The SN74CBTLV3126 device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull down resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The SN74CBTLV3126 device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull down resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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類型 標題 日期
* Data sheet SN74CBTLV3126 Low-Voltage Quadruple FET Bus Switch datasheet (Rev. L) PDF | HTML 2022年 8月 24日
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022年 6月 2日
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021年 12月 1日
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021年 1月 6日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
More literature Digital Bus Switch Selection Guide (Rev. A) 2004年 11月 10日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Bus FET Switch Solutions for Live Insertion Applications 2003年 2月 7日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 1998年 12月 1日

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LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

使用指南: PDF
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模擬型號

HSPICE Model for SN74CBTLV3126

SCDJ029.ZIP (96 KB) - HSpice Model
模擬型號

SN74CBTLV3126 IBIS Model

SCDM079.ZIP (25 KB) - IBIS Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 14 Ultra Librarian
SSOP (DBQ) 16 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian

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