TPA5051
- Digital Audio Format: 16-24-bit I2S, Right-Justified, Left-Justified
- I2C Bus Controlled
- Dual Serial Input Ports
- Delay Time: 85 ms/ch at fs = 48 kHz
- Delay Resolution: One Sample
- Delay Memory Cleared on Power-Up or After Delay Changes
- Eliminates Erroneous Data on Output
- 3.3 V Operation With 5 V Tolerant I/O and I2C Control
- Supports Audio Bit Clock Rates of 32 to 64 fs with fs = 32 kHz-192 kHz
- No External Crystal or Oscillator Required
- All Internal Clocks Generated From the Audio Clock
- Independent Clocks for Each Audio Input
- Surface Mount 4mm × 4mm, 16-pin QFN Package
- APPLICATIONS
- High Definition Lip-Sync Delay
- Flat Panel TV Lip-Sync Delay
- Home Theater Rear Channel Effects
- Wireless Speaker Front-Channel Synchronization
The TPA5051 accepts two serial audio inputs, buffers the data for a selectable period of time, and outputs the delayed audio data on two serial outputs. One device allows delay of up to 85 ms/ch (fs = 48 kHz) to synchronize the audio stream to the video stream in systems with complex video processing algorithms. If more delay is needed, the devices can be connected in series. Independent clocks can be used for each audio input.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Four Channel Digital Audio Lip-Sync Delay with I2C Control datasheet (Rev. A) | 2006年 7月 20日 | |
| EVM User's guide | TPA5051EVM - User Guide | 2006年 7月 20日 |
設計與開發
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TPA5051EVM — TPA5051 評估模組 (EVM)
The TPA5051 evaluation module (EVM) consists of a single TPA5051 audio delay device, along with other external components mounted on a printed-circuit board (PCB) that can be used to independently delay two digital audio streams. Each digital audio stream consists of a left and right channel, both (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 引腳 | 下載 |
|---|---|---|
| VQFN (RSA) | 16 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。