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TPS51200-Q1

現行

汽車類汲極/源極 DDR 終端穩壓器

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TPS51200A-Q1 現行 汲極和源極 DDR 終端穩壓器 This product has added features for increased robustness.

TPS51200-Q1

現行
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產品詳細資料

Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (max) (V) 1.8 Features S3/S5 Support Iq (typ) (mA) 0.5 Rating Automotive Operating temperature range (°C) -40 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (max) (V) 1.8 Features S3/S5 Support Iq (typ) (mA) 0.5 Rating Automotive Operating temperature range (°C) -40 to 125 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
VSON (DRC) 10 9 mm² 3 x 3
  • Qualified for Automotive Applications
  • AEC-Q100 Test Guidance With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink/Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad
  • Qualified for Automotive Applications
  • AEC-Q100 Test Guidance With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink/Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad

The TPS51200-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200-Q1 device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The TPS51200-Q1 device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200-Q1 device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200-Q1 device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.

The TPS51200-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200-Q1 device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The TPS51200-Q1 device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200-Q1 device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200-Q1 device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.
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類型 標題 日期
* Data sheet TPS51200-Q1 Sink and Source DDR Termination Regulator datasheet (Rev. C) PDF | HTML 2016年 7月 25日
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020年 7月 9日
Technical article Improving DDR Memory Performance in Automotive Applications PDF | HTML 2017年 6月 22日
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 2010年 4月 28日
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 2010年 4月 20日
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 2010年 3月 31日
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 2010年 3月 26日
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 2010年 3月 26日
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 2010年 3月 26日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TPS51200EVM — TPS51200 汲極源極 DDR 終端穩壓器

TPS51200EVM 評估板 HPA322A 旨在評估 TI 成本最佳化的 DDR/DDR2/DDR3/LP DDR3 VTT 終端穩壓器 TPS51200 的性能和特性。TPS51200 旨在為 DDR 記憶體提供適當的終止電壓與 10-mA 緩衝參考電壓，該電壓涵蓋 DDR (2.5 V/1.25 V)、DDR2 (1.8 V/0.9 V)、DDR3 (1.5 V/0.75 V)、LP DDR3 (1.2 V/0.6 V) 規格，且僅需最少外部零組件。

使用指南: PDF
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模擬型號

TPS51200 PSpice Average Model

SLVM069.ZIP (30 KB) - PSpice Model
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模擬型號

TPS51200 PSpice Transient Model (Rev. A)

SLVM068A.ZIP (38 KB) - PSpice Model
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模擬型號

TPS51200 TINA-TI Average Reference Design

SLUM150.TSC (755 KB) - TINA-TI Reference Design
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模擬型號

TPS51200 TINA-TI Average Spice Model

SLUM151.ZIP (17 KB) - TINA-TI Spice Model
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模擬型號

TPS51200 TINA-TI Start-Up Transient Reference Design

SLUM148.TSC (127 KB) - TINA-TI Reference Design
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模擬型號

TPS51200 TINA-TI Transient Spice Model

SLUM149.ZIP (18 KB) - TINA-TI Spice Model
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參考設計

TIDA-01425 — 具有乙太網路和 CAN 的車用獨立閘道參考設計

The TIDA-01425 is a subsystem reference design for automotive gateways focused on increasing bandwidth and processing power in gateway applications. The design implements Ethernet physical layer transceivers (PHYs) for increased bandwidth along with an automotive processor for greater processing (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-080004 — 適用於擴增實境抬頭顯示的電子與 LED 驅動器參考設計

This reference design provides an electronics subsystem designed to drive an automotive augmented reality (AR) head-up display (HUD). DLP® technology enables bright, crisp, highly saturated head-up displays that project critical driving information onto the windshield of the car, reducing (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00805 — 適用於 ADAS 和資訊娛樂系統的車用無電池處理器電源參考設計

The TIDA-00805 reference design is an off-battery automotive power solution targeting processors in advanced driver assistance systems (ADAS) like surround view, front camera and driver monitoring, as well as infotainment systems such as cluster and head unit. The design operates directly from a (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00801 — 車用無電池資訊娛樂系統處理器電源參考設計

The TIDA-00801 reference design is a full off-battery to point of load power solution supporting input voltages as low as 2V.  It uses the Boost plus Buck DC/DC regulator TPS43330A-Q1 supporting an  input voltage range of  2V to 40V and allowing the design to support not only (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00346 — 適用於入門級核心應用處理器架構 ADAS 系統的成本最佳化電源供應器解決方案

The TIDA-00346 design provides the power supply rails necessary for typical  entry-level application processors in automotive advanced driver assistance systems (ADAS) applications.  The design uses several individual DC/DC voltage regulators as well as load switches and linear regulators (...)
Test report: PDF
電路圖: PDF
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