TRS3253E-EP
- VL Pin for Compatibility With
Mixed-Voltage Systems Down to 1.8 V on Logic
Side - Enhanced ESD Protection on RIN Inputs and
DOUT Outputs- ±8 kV IEC 61000-4-2 Air-Gap Discharge
- ±8 kV IEC 61000-4-2 Contact Discharge
- ±15 kV Human-Body Model
- Low 300-µA Supply Current
- Specified 1000-kbps Data Rate
- Auto Powerdown Plus Feature
The TRS3253E is a three-driver and five-receiver RS-232 interface device, with split supply pins for mixed-signal operations. All RS-232 inputs and outputs are protected to ±8 kV using the IEC 61000-4-2 Air-Gap Discharge method, ±8 kV using the IEC 61000-4-2 Contact Discharge method, and ±15 kV using the Human-Body Model.
The charge pump requires only four small 0.1-µF capacitors for operation from a 3.3-V supply. The TRS3253E is capable of running at data rates up to 1000 kbps, while maintaining RS-232-compliant output levels.
The TRS3253E has a unique VL pin that allows operation in mixed-logic voltage systems. Both driver in (DIN) and receiver out (ROUT) logic levels are pin programmable through the VL pin. This eliminates the need for additional voltage level shifter while interfacing with low-voltage microcontroller or UARTs. The TRS3253E is available in a space-saving QFN package (4 mm × 4 mm RSM).
Auto-powerdown plus can be disabled when FORCEON and FORCEOFF are high. With auto-powerdown plus enabled, the device activates automatically when a valid signal is applied to any receiver or driver input. INVALID is high (valid data) if any receiver input voltage is greater than 2.7 V or less than –2.7 V, or has been between –0.3 V and 0.3 V for less than 30 µs. INVALID is low (invalid data) if all receiver input voltages are between –0.3 V and 0.3 V for more than 30 µs. Refer to for receiver input levels.
您可能會感興趣的類似產品
功能相同,但引腳輸出與所比較的裝置不同
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | RS-232 Transceiver With Split Supply Pin for Logic Side, TRS3253E-EP datasheet | 2013年 12月 27日 | |
| * | VID | TRS3253E-EP VID V6213621 | 2016年 6月 21日 | |
| * | Radiation & reliability report | 74AHC1G126MDCKTEP Reliability Report | 2014年 12月 16日 | |
| * | Radiation & reliability report | TRS3253EMRSMREP Reliability Report | 2014年 12月 16日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前,建立完整的終端設備設計和解決方案原型,進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中,您可以搜尋 TI (...)
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RSM) | 32 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。