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UCC27524A-Q1

現行

具有 5-V UVLO 和負輸入電壓處理功能的汽車 5-A/5-A 雙通道閘極驅動器

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產品規格表

UCC27524A-Q1

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C4B
  • Industry-Standard Pin Out
  • Two Independent Gate-Drive Channels
  • 5-A Peak Source and Sink-Drive Current
  • Independent Enable Function for Each Output
  • TTL and CMOS-Compatible Logic Threshold
    Independent of Supply Voltage
  • Hysteretic-Logic Thresholds for High-Noise
    Immunity
  • Ability to Handle Negative Voltages (–5 V) at
    Inputs
  • Inputs and Enable Pin-Voltage Levels Not
    Restricted by VDD Pin Bias Supply Voltage
  • 4.5-V to 18-V Single-Supply Range
  • Outputs Held Low During VDD-UVLO, (ensures
    glitch-free operation at power-up and power-
    down)
  • Fast Propagation Delays (13-ns typical)
  • Fast Rise and Fall Times (7-ns and 6-ns typical)
  • 1-ns Typical Delay Matching Between 2-Channels
  • Ability to Parallel Two Outputs for High-Drive
    Current
  • Outputs Held in LOW When Inputs are Floating
  • SOIC-8 and MSOP-8 PowerPad™ Package Options
  • Operating Temperature Range of –40°C to 140°C
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C4B
  • Industry-Standard Pin Out
  • Two Independent Gate-Drive Channels
  • 5-A Peak Source and Sink-Drive Current
  • Independent Enable Function for Each Output
  • TTL and CMOS-Compatible Logic Threshold
    Independent of Supply Voltage
  • Hysteretic-Logic Thresholds for High-Noise
    Immunity
  • Ability to Handle Negative Voltages (–5 V) at
    Inputs
  • Inputs and Enable Pin-Voltage Levels Not
    Restricted by VDD Pin Bias Supply Voltage
  • 4.5-V to 18-V Single-Supply Range
  • Outputs Held Low During VDD-UVLO, (ensures
    glitch-free operation at power-up and power-
    down)
  • Fast Propagation Delays (13-ns typical)
  • Fast Rise and Fall Times (7-ns and 6-ns typical)
  • 1-ns Typical Delay Matching Between 2-Channels
  • Ability to Parallel Two Outputs for High-Drive
    Current
  • Outputs Held in LOW When Inputs are Floating
  • SOIC-8 and MSOP-8 PowerPad™ Package Options
  • Operating Temperature Range of –40°C to 140°C

The UCC27524A-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A-Q1 device is a variant of the UCC2752x family. The UCC27524A-Q1 device adds the ability to handle –5 V directly at the input pins for increased robustness. The UCC27524A-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A-Q1 device is capable of delivering high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 13 ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

The UCC27524A-Q1 devices is available in SOIC-8 (D) and MSOP-PowerPAD-8 with exposed pad (DGN) packages.

The UCC27524A-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A-Q1 device is a variant of the UCC2752x family. The UCC27524A-Q1 device adds the ability to handle –5 V directly at the input pins for increased robustness. The UCC27524A-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A-Q1 device is capable of delivering high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 13 ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

The UCC27524A-Q1 devices is available in SOIC-8 (D) and MSOP-PowerPAD-8 with exposed pad (DGN) packages.
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UCC27624-Q1 現行 具有 4-V UVLO、30-V VDD 與低傳播延遲的車用 5-A/5-A 雙通道閘極驅動器 Next generation with better negative voltage handling and robustness

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類型 標題 日期
* Data sheet UCC27524A-Q1 Dual 5-A, High-Speed, Low-Side Gate Driver With Negative Input Voltage Capability datasheet (Rev. B) PDF | HTML 2015年 7月 24日
Application note Why use a Gate Drive Transformer? PDF | HTML 2024年 3月 4日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 2018年 10月 29日
White paper Driving the future of HEV/EV with high-voltage solutions (Rev. B) 2018年 5月 16日
Technical article Are you on-board? Demystifying EV charging systems PDF | HTML 2017年 7月 31日

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模擬型號

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SLUM257.TSC (89 KB) - TINA-TI Reference Design
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