計算工具
UCC27525
- Industry-Standard Pinout
- Two Independent Gate-Drive Channels
- 5-A Peak Source and Sink-Drive Current
- Independent-Enable Function for Each Output
- TTL and CMOS Compatible Logic Threshold
Independent of Supply Voltage - Hysteretic-Logic Thresholds for High Noise
Immunity - Inputs and Enable Pin-Voltage Levels Not
Restricted by VDD Pin Bias Supply Voltage - 4.5-V to 18-V Single-Supply Range
- Outputs Held Low During VDD-UVLO, (Ensures
Glitch-Free Operation at Power up and Power
Down) - Fast Propagation Delays (13-ns Typical)
- Fast Rise and Fall Times (7-ns and 6-ns Typical)
- 1-ns Typical Delay Matching Between Two
Channels - Two Outputs are in Parallel for Higher Drive
Current - Outputs Held Low When Inputs Floating
- PDIP (8), SOIC (8), MSOP (8) PowerPAD™ and
3-mm × 3-mm WSON-8 Package Options - Operating Temperature Range of –40°C to 140°C
The UCC2752x family of devices are dual-channel, high-speed, low-side gate-driver devices capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC2752x can deliver high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 13 ns). In addition, the drivers feature matched internal propagation delays between the two channels. These delays are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with one input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.
The UCC2752x family provide the combination of three standard logic options – dual inverting, dual noninverting, one inverting and one noninverting driver. UCC27526 features a dual input design which offers flexibility of both inverting (IN– pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN– pin controls the state of the driver output. The unused input pin is used for enable and disable functions. For safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family ensure that outputs are held LOW when input pins are in floating condition. The UCC27523, UCC27524, and UCC27525 devices feature Enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.
UCC2752x family of devices are available in SOIC-8 (D), MSOP-8 with exposed pad (DGN) and 3-mm × 3-mm WSON-8 with exposed pad (DSD) packages. UCC27524 is also offered in PDIP-8 (P) package. UCC27526 is only offered in 3-mm × 3-mm WSON (DSD) package.
技術文件
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檢視所有 11 | 類型 | 名稱 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | UCC2752x Dual 5-A High-Speed, Low-Side Gate Driver datasheet (Rev. G) | PDF | HTML | 2015年 4月 1日 |
| 技術文章 | Managing power-supply noise with a 30-V gate driver | 2021年 12月 7日 | ||
| Application note | External Gate Resistor Selection Guide (Rev. A) | 2020年 2月 28日 | ||
| Application note | Understanding Peak IOH and IOL Currents (Rev. A) | 2020年 2月 28日 | ||
| Application note | Improving Efficiency of DC-DC Conversion through Layout | 2019年 5月 7日 | ||
| More literature | Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) | 2018年 10月 29日 | ||
| 技術文章 | How to achieve higher system robustness in DC drives, part 3: minimum input pulse | 2018年 9月 19日 | ||
| Selection guide | Power Management Guide 2018 (Rev. R) | 2018年 6月 25日 | ||
| 技術文章 | How to achieve higher system robustness in DC drives, part 2: interlock and deadtime | 2018年 5月 30日 | ||
| 技術文章 | How to achieve higher system robustness in DC drives, part 1: negative voltage | 2018年 4月 17日 | ||
| Application note | Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole | 2018年 3月 16日 |
設計與開發
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開發板
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使用指南: PDF
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計
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Design guide: PDF
| 封裝 | 引腳 | 下載 |
|---|---|---|
| HVSSOP (DGN) | 8 | 檢視選項 |
| SOIC (D) | 8 | 檢視選項 |
| WSON (DSD) | 8 | 檢視選項 |
訂購與品質
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- 認證摘要
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