計算工具
UCC27532-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 1
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C4B
- Low-Cost Gate Driver (offering optimal solution
for driving FET and IGBTs) - Superior Replacement to Discrete Transistor Pair
Drive (providing easy interface with controller) - CMOS Compatible Input-Logic Threshold (becomes
fixed at VDD above 18 V) - Split Outputs Allow Separate Turnon and Turnoff
Tuning - Enable with Fixed TTL Compatible Threshold
- High 2.5-A Source and 5-A Sink Peak-Drive Currents
at 18-V VDD - Wide VDD Range From 10 V up to 35 V
- Input Pins Capable of Withstanding up to –5-V
DC Below Ground - Output Held Low When Inputs are Floating or During
VDD UVLO - Fast Propagation Delays (17-ns typical)
- Fast Rise and Fall Times
(15-ns and 7-ns typical with 1800-pF Load) - Undervoltage Lockout (UVLO)
- Used as a High-Side or Low-Side Driver (if designed
with proper bias and signal isolation) - Low-Cost Space-Saving 6-Pin DBV (SOT-23) Package
- Operating Temperature Range of –40°C to 140°C
The UCC27532-Q1 device is a single-channel high-speed gate driver capable of effectively driving MOSFET and IGBT power switches by up to 2.5-A source and 5-A sink (asymmetrical drive) peak current. Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turnon effect. The UCC27532-Q1 device also features a split-output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates.
The driver has rail-to-rail drive capability and an extremely-small propagation delay of 17 ns (typically).
The UCC27532-Q1 device has a CMOS-input threshold-centered 55% rise and 45% fall in regards of VDD at VDD below or equal 18 V. When VDD is above 18 V, the input threshold remains fixed at the maximum level.
The driver has an EN pin with a fixed TTL-compatible threshold. EN is internally pulled up; pulling EN low disables driver, while leaving it open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN pin.
Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the Timing Diagram, Input/Output Logic Truth Table, and Typical Application Diagrams.
Internal circuitry on the VDD pin provides an undervoltage-lockout function that holds the output low until the VDD supply voltage is within operating range.
The UCC27532-Q1 driver is offered in a 6-pin standard SOT-23 (DBV) package. The device operates over a wide temperature range of –40°C to 140°C.
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檢視所有 5 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | UCC27532-Q1 2.5-A and 5-A, 35-VMAX VDD FET and IGBT Single-Gate Driver datasheet (Rev. A) | 2014年 1月 2日 | |
| Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020年 2月 28日 | ||
| Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020年 2月 28日 | ||
| Application brief | High-Side Cutoff Switches for High-Power Automotive Applications (Rev. A) | 2018年 11月 26日 | ||
| More literature | Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) | 2018年 10月 29日 |
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| 封裝 | 引腳 | 下載 |
|---|---|---|
| SOT-23 (DBV) | 6 | 檢視選項 |
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