Wafer-level Chip-Scale Package FAQs
Includes answers to questions about TI’s WCSP packaging technology’s advantages and proper practices to work with WCSP devices.
What is WCSP?
WCSP, also referred to as DSBGA, is packaging technology that includes the following features:
- Package size is equal to die size
- Smallest footprint per I/O count
- Interconnect layout available in 0.3, 0.34, 0.4, and 0.5mm pitch
Should I use Non-Solder Mask Defined (NSMD) or Solder Mask Defined (SMD) PCB pads with WSCP packages?
Two types of PCB land patterns are used for surface mount packages:
- Non-solder mask defined (NSMD)
- Solder mask defined (SMD)
- For WCSP, the NSMD configuration is preferred due to its tighter control of the copper etch process and a reduction in the stress concentration points on the PCB side compared to the SMD configuration.
- A copper layer of less than or equal to 1 oz. is recommended to achieve higher solder join stand-off. Greater than 1 oz. of copper thickness causes a lower effective solder joint stand-off, which may adversely impact solder joint reliability.
- For the NSMD configuration, the trace width at the connection to the land pad should not exceed 66 percent of the pad diameter.
Are there any guidelines for WCSP handling?
Where can I find TI WCSP BSGA packages?
A complete list of TI packages for Die-Size Ball Grid Array (WCSP) (DSBGA) can be found here, where you can review each package’s drawing and specifications such as pin count, pitch, and dimension. There is also an option to enter your parametric requirements, and search packages that meet the dimension needs of your design.