Product details

Output options Adjustable Output, Fixed Output Iout (Max) (A) 1 Vin (Max) (V) 10 Vin (Min) (V) 2.7 Vout (Max) (V) 5.5 Vout (Min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 5 Noise (uVrms) 55 Iq (Typ) (mA) 0.08 Thermal resistance θJA (°C/W) 106.9 Rating Catalog Load capacitance (Min) (µF) 10 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 2 PSRR @ 100 KHz (dB) 29 Dropout voltage (Vdo) (Typ) (mV) 230 Operating temperature range (C) -40 to 125
Output options Adjustable Output, Fixed Output Iout (Max) (A) 1 Vin (Max) (V) 10 Vin (Min) (V) 2.7 Vout (Max) (V) 5.5 Vout (Min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 5 Noise (uVrms) 55 Iq (Typ) (mA) 0.08 Thermal resistance θJA (°C/W) 106.9 Rating Catalog Load capacitance (Min) (µF) 10 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 2 PSRR @ 100 KHz (dB) 29 Dropout voltage (Vdo) (Typ) (mV) 230 Operating temperature range (C) -40 to 125
HTSSOP (PWP) 20 42 mm² 6.5 x 6.4 SOIC (D) 8 19 mm² 3.91 x 4.9
  • 1 A Low-Dropout Voltage Regulator
  • Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions
  • Dropout Voltage Down to 230 mV at 1 A (TPS76750)
  • Ultralow 85 µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • Open Drain Power-On Reset With 200-ms Delay (See TPS768xx for PG Option)
  • 8-Pin SOIC and 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection

All trademarks are the property of their respective owners.

  • 1 A Low-Dropout Voltage Regulator
  • Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions
  • Dropout Voltage Down to 230 mV at 1 A (TPS76750)
  • Ultralow 85 µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • Open Drain Power-On Reset With 200-ms Delay (See TPS768xx for PG Option)
  • 8-Pin SOIC and 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection

All trademarks are the property of their respective owners.

This device is designed to have a fast transient response and be stable with 10 µF low ESR capacitors. This combination provides high performance at a reasonable cost.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
230 mV at an output current of 1 A for the TPS76750) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically
85 µA over the full range of output current, 0 mA to
1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C.

The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.

The TPS767xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5.0-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS767xx family is available in 8-pin SOIC and 20-pin PWP packages.

This device is designed to have a fast transient response and be stable with 10 µF low ESR capacitors. This combination provides high performance at a reasonable cost.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
230 mV at an output current of 1 A for the TPS76750) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically
85 µA over the full range of output current, 0 mA to
1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C.

The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.

The TPS767xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5.0-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS767xx family is available in 8-pin SOIC and 20-pin PWP packages.

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Technical documentation

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Type Title Date
* Data sheet TPS767xxQ Fast-Transient-Response 1-A Low-Dropout Linear Regulators datasheet (Rev. J) PDF | HTML 06 Aug 2015
Application note LDO Noise Demystified (Rev. B) PDF | HTML 18 Aug 2020
Application note PowerPAD™ Thermally Enhanced Package (Rev. H) 06 Jul 2018
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 09 Aug 2017
User guide Voltage-Controlled Amplifier Evaluation Kit 25 Aug 2008
Application note Power Supply Sequencing Solutions for Dual Supply Voltage DSPs (Rev. A) 05 Jul 2000

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

TPS76715Q Unencrypted PSpice Transient Model

SLVMB12.ZIP (2 KB) - PSpice Model
Simulation model

TPS76715Q PSpice Transient Model

SLVMB13.ZIP (83 KB) - PSpice Model
Simulation model

TPS76733Q Unencrypted PSpice Transient Model

SLVMB14.ZIP (2 KB) - PSpice Model
Simulation model

TPS76733Q PSpice Transient Model

SLVMB15.ZIP (78 KB) - PSpice Model
Simulation model

TPS76727Q PSpice Transient Model

SLVMB16.ZIP (80 KB) - PSpice Model
Simulation model

TPS76727Q Unencrypted PSpice Transient Model

SLVMB17.ZIP (2 KB) - PSpice Model
Simulation model

TPS76728Q PSpice Transient Model

SLVMB18.ZIP (83 KB) - PSpice Model
Simulation model

TPS76728Q Unencrypted PSpice Transient Model

SLVMB19.ZIP (2 KB) - PSpice Model
Simulation model

TPS76725Q PSpice Transient Model

SLVMB20.ZIP (80 KB) - PSpice Model
Simulation model

TPS76725Q Unencrypted PSpice Transient Model

SLVMB21.ZIP (2 KB) - PSpice Model
Simulation model

TPS76750Q Unencrypted PSpice Transient Model

SLVMB22.ZIP (2 KB) - PSpice Model
Simulation model

TPS76750Q PSpice Transient Model

SLVMB23.ZIP (81 KB) - PSpice Model
Simulation model

TPS76718Q PSpice Transient Model

SLVMB24.ZIP (80 KB) - PSpice Model
Simulation model

TPS76718Q Unencrypted PSpice Transient Model

SLVMB25.ZIP (2 KB) - PSpice Model
Simulation model

TPS76730Q Unencrypted PSpice Transient Model

SLVMB26.ZIP (2 KB) - PSpice Model
Simulation model

TPS76730Q PSpice Transient Model

SLVMB27.ZIP (83 KB) - PSpice Model
Simulation model

TPS76701Q Unencrypted PSpice Transient Model

SLVMB34.ZIP (3 KB) - PSpice Model
Simulation model

TPS76701Q PSpice Transient Model

SLVMB35.ZIP (89 KB) - PSpice Model
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Package Pins Download
HTSSOP (PWP) 20 View options
SOIC (D) 8 View options

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