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TPS767

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1-A, 10-V, low-dropout voltage regulator with enable & RESET with delay

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1-A, 10-V, low-dropout voltage regulator with enable & RESET with delay

TPS767

ACTIVE
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Product details

Parameters

Output options Adjustable Output, Fixed Output Iout (Max) (A) 1 Vin (Max) (V) 10 Vin (Min) (V) 2.7 Vout (Max) (V) 5.5 Vout (Min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 5 Noise (uVrms) 55 Iq (Typ) (mA) 0.08 Thermal resistance θJA (°C/W) 106.9 Load capacitance (Min) (µF) 10 Rating Catalog Regulated outputs (#) 1 Features Enable, Power Good Accuracy (%) 2 PSRR @ 100 KHz (dB) 29 Dropout voltage (Vdo) (Typ) (mV) 230 Operating temperature range (C) -40 to 125 open-in-new Find other Linear regulators (LDO)

Package | Pins | Size

HTSSOP (PWP) 20 42 mm² 6.5 x 6.4 SOIC (D) 8 19 mm² 3.91 x 4.9 open-in-new Find other Linear regulators (LDO)

Features

  • 1 A Low-Dropout Voltage Regulator
  • Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions
  • Dropout Voltage Down to 230 mV at 1 A (TPS76750)
  • Ultralow 85 µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • Open Drain Power-On Reset With 200-ms Delay (See TPS768xx for PG Option)
  • 8-Pin SOIC and 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection

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Description

This device is designed to have a fast transient response and be stable with 10 µF low ESR capacitors. This combination provides high performance at a reasonable cost.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
230 mV at an output current of 1 A for the TPS76750) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically
85 µA over the full range of output current, 0 mA to
1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C.

The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.

The TPS767xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5.0-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS767xx family is available in 8-pin SOIC and 20-pin PWP packages.

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Technical documentation

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Type Title Date
* Data sheet TPS767xxQ Fast-Transient-Response 1-A Low-Dropout Linear Regulators datasheet (Rev. J) Aug. 06, 2015
Application note LDO Noise Demystified (Rev. B) Aug. 18, 2020
Technical article LDO basics: capacitor vs. capacitance Aug. 01, 2018
Technical article LDO Basics: Preventing reverse current Jul. 25, 2018
Application note PowerPAD™ Thermally Enhanced Package (Rev. H) Jul. 06, 2018
Technical article LDO basics: introduction to quiescent current Jun. 20, 2018
Application note LDO PSRR Measurement Simplified (Rev. A) Aug. 09, 2017
Technical article LDO basics: noise – part 1 Jun. 14, 2017
User guide Voltage-Controlled Amplifier Evaluation Kit Aug. 25, 2008
Application note Power Supply Sequencing Solutions for Dual Supply Voltage DSPs (Rev. A) Jul. 05, 2000

Design & development

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Design tools & simulation

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Reference designs

REFERENCE DESIGNS Download
Altera Arria V FPGA Power Supply Reference Design
PMP9357 — The PMP9357 reference design is a complete power solution for Altera's Arria V series FPGAs.  This design uses several TPS54620 synchronous step down converters, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  To provide correct power (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Direct Down-Conversion System with I/Q Correction
TIDA-00078 — The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent I/Q (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Wide-Bandwidth and High-Voltage Arbitrary Waveform Generator Front End
TIDA-00075 — This design shows how to use an active interface with the current sink output of the DAC5682Z - typical applications for this include front ends for arbitrary waveform generators. The EVM includes the DAC5682Z for digital-to-analog conversion, an OPA695 to demonstrate an active interface (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Wideband RF-to-Digital Complex Receiver-Feedback Signal Chain
TIDA-00074 — This is a wideband complex-receiver reference design and evaluation platform that is ideally suited for use as a feedback receiver for transmitter digital predistortion. The EVM signal chain is ideal for high intermediate-frequency (IF) complex-feedback applications and contains a complex (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Dual-Wideband RF-to-Digital Receiver Design
TIDA-00073 — The TSW1265EVM is an example design of a wideband RF to digital dual receiver solution capable of digitizing up to 125MHz of spectrum. The system provides a reference on how to use the ADS4249, LMH6521, LMK0480x, and a dual mixer to achieve this.  This reference EVEM coupled with a capture card (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Basestation Transceiver with DPD Feedback Path
TIDA-00068 — The design is for a small cell base station development platform.  It provides two real receive paths, two complex transmit paths, and a shared real feedback path.  This design has macro basestation performance, but with small cell base station footprint.  The current design handles (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
HTSSOP (PWP) 20 View options
SOIC (D) 8 View options

Ordering & quality

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