DDR-less EtherCAT® Slave on AMIC110 Reference Design


Design files


EtherCAT® (Ethernet for Control Automation Technology) continuously grows to establish itself as a dominant, industrial, Ethernet network. The DDR-less EtherCAT reference design serves as a reference design for a completely new and low-cost, DDR-less, EtherCAT slave implementation on the AMIC110, a multiprotocol industrial communications system on a chip (SoC). This reference design showcases the ability to run a full EtherCAT slave stack entirely on the internal memory of the SoC. Significant system bill of materials (BOM) and board savings are achieved with this reference design by eliminating an external ASIC and DDR.  Additionally, applications such as connected industrial drives and communications modules can significantly benefit from the faster speeds that are achieved by eliminating external memory transfers for EtherCAT.

  • Entire EtherCAT slave stack is hosted on internal memory
  • Passes EtherCAT Slave Conformance Testing Tool (CTT) from EtherCAT Technology Group (ETG)
  • Eight Fieldbus Memory Management Units (FMMUs) and Sync Managers (SMs) supported by PRU-ICSS firmware
  • Enhanced link-loss detection for loop control
  • Helps improve system performance with removal of latencies associated with external memory accesses

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUE46.PDF (519 K)

Reference design overview and verified performance test data

SPRR278.ZIP (1897 K)

Detailed schematic diagram for design layout and components

SPRR279.PDF (91 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

SPRR280.ZIP (10806 K)

Detailed overview of design layout for component placement

SPRR276.PDF (636 K)

PCB layer plot file used for generating PCB design layout

SPRR277.PDF (629 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

Arm-based processors

AMIC110Sitara processor: Arm Cortex-A8, 10+ Ethernet protocols

Data sheet document-pdfAcrobat PDF open-in-new HTML
Ethernet PHYs

DP83822HExtended temperature, robust low-power 10/100-Mbps Ethernet PHY transceiver with 16-kV ESD

Data sheet document-pdfAcrobat PDF open-in-new HTML
Multi-channel ICs (PMIC)

TPS650250Configurable integrated power management (PMIC) with 3 DC/DC converters and 3 LDOs

Data sheet document-pdfAcrobat PDF open-in-new HTML

Start development


Evaluation board

TMDXICE110 – AMIC110 Industrial Communications Engine (ICE)

The AMIC110 Industrial Communications Engine (ICE) is a development platform targeted at industrial communications and industrial ethernet in particular. Key to the AMIC110 ICE is the Sitara AMIC110 SoC that features Arm® Cortex™-A8 processor along with the Programmable-Realtime Unit (...)

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Technical documentation

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Type Title Date
* Design guide EtherCAT DDR-less Reference Design Feb. 26, 2018

Related design resources

Software development

PRU-ICSS-INDUSTRIAL-SW PRU-ICSS Industrial Software for Sitara™ Processors

Reference designs

TIDA-00299 EtherCAT Slave and Multi-Protocol Industrial Ethernet Reference Design

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