EtherCAT® (Ethernet for Control Automation Technology) continuously grows to establish itself as a dominant, industrial, Ethernet network. The DDR-less EtherCAT reference design serves as a reference design for a completely new and low-cost, DDR-less, EtherCAT slave implementation on the AMIC110, a multiprotocol industrial communications system on a chip (SoC). This reference design showcases the ability to run a full EtherCAT slave stack entirely on the internal memory of the SoC. Significant system bill of materials (BOM) and board savings are achieved with this reference design by eliminating an external ASIC and DDR. Additionally, applications, such as connected industrial drives and communications modules, can significantly benefit from the faster speeds that are achieved by eliminating external memory transfers for EtherCAT.
- Entire EtherCAT slave stack is hosted on internal memory
- Passes EtherCAT Slave Conformance Testing Tool (CTT) from EtherCAT Technology Group (ETG)
- Eight Fieldbus Memory Management Units (FMMUs) and Sync Managers (SMs) supported by PRU-ICSS firmware
- Enhanced link-loss detection for loop control
- Helps improve system performance with removal of latencies associated with external memory accesses