AMIC110

NFBGA (ZCZ)

324

—

Up to 300-MHz Sitara™ ARM^® Cortex^®-A8 32‑Bit RISC Processor
- NEON™ SIMD Coprocessor
- 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
- 256KB of L2 Cache With Error Correcting Code (ECC)
- 176KB of On-Chip Boot ROM
- 64KB of Dedicated RAM
- Emulation and Debug - JTAG
- Interrupt Controller (up to 128 Interrupt Requests)
On-Chip Memory (Shared L3 RAM)
- 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- Accessible to All Masters
- Supports Retention for Fast Wakeup
External Memory Interfaces (EMIF)
- mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
  - mDDR: 200-MHz Clock (400-MHz Data Rate)
  - DDR2: 266-MHz Clock (532-MHz Data Rate)
  - DDR3: 400-MHz Clock (800-MHz Data Rate)
  - DDR3L: 400-MHz Clock (800-MHz Data Rate)
  - 16-Bit Data Bus
  - 1GB of Total Addressable Space
  - Supports One x16 or Two x8 Memory Device Configurations
- General-Purpose Memory Controller (GPMC)
  - Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
  - Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
  - Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module (ELM)
  - Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
  - Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Supports Protocols such as EtherCAT^®, PROFIBUS, PROFINET, EtherNet/IP™, and More
- Two Programmable Real-Time Units (PRUs)
  - 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
  - 8KB of Instruction RAM With Single-Error Detection (Parity)
  - 8KB of Data RAM With Single-Error Detection (Parity)
  - Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
  - Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
- 12KB of Shared RAM With Single-Error Detection (Parity)
- Three 120-Byte Register Banks Accessible by Each PRU
- Interrupt Controller (INTC) for Handling System Input Events
- Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
- Peripherals Inside the PRU-ICSS:
  - One UART Port With Flow Control Pins, Supports up to 12 Mbps
  - One Enhanced Capture (eCAP) Module
  - Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
  - One MDIO Port
Power, Reset, and Clock Management (PRCM) Module
- Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
- Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Clocks
  - Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
  - Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
  - Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock ⁽¹⁾)
- Power
  - Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
  - Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX]⁽¹⁾, Peripherals and Infrastructure [PER])
  - Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
  - Dynamic Voltage Frequency Scaling (DVFS)
Real-Time Clock (RTC)
- Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
- Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
- Independent Power-on-Reset (RTC_PWRONRSTn) Input
- Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
- Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
- Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
Peripherals
- Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
- Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
  - Integrated Switch
  - Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
  - Ethernet MACs and Switch Can Operate Independent of Other Functions
  - IEEE 1588v1 Precision Time Protocol (PTP)
- Up to Two Controller-Area Network (CAN) Ports
  - Supports CAN Version 2 Parts A and B
- Up to Two Multichannel Audio Serial Ports (McASPs)
  - Transmit and Receive Clocks up to 50 MHz
  - Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
  - Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
  - Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
  - FIFO Buffers for Transmit and Receive (256 Bytes)
- Up to Six UARTs
  - All UARTs Support IrDA and CIR Modes
  - All UARTs Support RTS and CTS Flow Control
  - UART1 Supports Full Modem Control
- Up to Two Master and Slave McSPI Serial Interfaces
  - Up to Two Chip Selects
  - Up to 48 MHz
- Up to Three MMC, SD, SDIO Ports
  - 1-, 4- and 8-Bit MMC, SD, SDIO Modes
  - MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
  - Up to 48-MHz Data Transfer Rate
  - Supports Card Detect and Write Protect
  - Complies With MMC4.3, SD, SDIO 2.0 Specifications
- Up to Three I²C Master and Slave Interfaces
  - Standard Mode (up to 100 kHz)
  - Fast Mode (up to 400 kHz)
- Up to Four Banks of General-Purpose I/O (GPIO) Pins
  - 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
  - GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
- Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
- Eight 32-Bit General-Purpose Timers
  - DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
  - DMTIMER4–DMTIMER7 are Pinned Out
- One Watchdog Timer
- 12-Bit Successive Approximation Register (SAR) ADC
  - 200K Samples per Second
  - Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
- Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
  - Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
  - Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
Device Identification
- Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
  - Production ID
  - Device Part Number (Unique JTAG ID)
  - Device Revision (Readable by Host ARM)
Debug Interface Support
- JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
- Supports Device Boundary Scan
- Supports IEEE 1500
DMA
- On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
  - Transfers to and from On-Chip Memories
  - Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
Inter-Processor Communication (IPC)
- Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
  - Mailbox Registers that Generate Interrupts
    - Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
  - Spinlock has 128 Software-Assigned Lock Registers
Boot Modes
- Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
Package:
- 324-Pin S-PBGA-N324 Package
  (ZCZ Suffix), 0.80-mm Ball Pitch

⁽¹⁾The GFX [SGX530] and LCD modules are not supported for this family of devices, but the "LCD" and "GFX" names are still present in some PLL, power domain, or supply voltage names.

Up to 300-MHz Sitara™ ARM^® Cortex^®-A8 32‑Bit RISC Processor
- NEON™ SIMD Coprocessor
- 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
- 256KB of L2 Cache With Error Correcting Code (ECC)
- 176KB of On-Chip Boot ROM
- 64KB of Dedicated RAM
- Emulation and Debug - JTAG
- Interrupt Controller (up to 128 Interrupt Requests)
On-Chip Memory (Shared L3 RAM)
- 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- Accessible to All Masters
- Supports Retention for Fast Wakeup
External Memory Interfaces (EMIF)
- mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
  - mDDR: 200-MHz Clock (400-MHz Data Rate)
  - DDR2: 266-MHz Clock (532-MHz Data Rate)
  - DDR3: 400-MHz Clock (800-MHz Data Rate)
  - DDR3L: 400-MHz Clock (800-MHz Data Rate)
  - 16-Bit Data Bus
  - 1GB of Total Addressable Space
  - Supports One x16 or Two x8 Memory Device Configurations
- General-Purpose Memory Controller (GPMC)
  - Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
  - Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
  - Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module (ELM)
  - Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
  - Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Supports Protocols such as EtherCAT^®, PROFIBUS, PROFINET, EtherNet/IP™, and More
- Two Programmable Real-Time Units (PRUs)
  - 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
  - 8KB of Instruction RAM With Single-Error Detection (Parity)
  - 8KB of Data RAM With Single-Error Detection (Parity)
  - Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
  - Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
- 12KB of Shared RAM With Single-Error Detection (Parity)
- Three 120-Byte Register Banks Accessible by Each PRU
- Interrupt Controller (INTC) for Handling System Input Events
- Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
- Peripherals Inside the PRU-ICSS:
  - One UART Port With Flow Control Pins, Supports up to 12 Mbps
  - One Enhanced Capture (eCAP) Module
  - Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
  - One MDIO Port
Power, Reset, and Clock Management (PRCM) Module
- Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
- Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Clocks
  - Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
  - Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
  - Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock ⁽¹⁾)
- Power
  - Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
  - Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX]⁽¹⁾, Peripherals and Infrastructure [PER])
  - Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
  - Dynamic Voltage Frequency Scaling (DVFS)
Real-Time Clock (RTC)
- Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
- Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
- Independent Power-on-Reset (RTC_PWRONRSTn) Input
- Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
- Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
- Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
Peripherals
- Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
- Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
  - Integrated Switch
  - Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
  - Ethernet MACs and Switch Can Operate Independent of Other Functions
  - IEEE 1588v1 Precision Time Protocol (PTP)
- Up to Two Controller-Area Network (CAN) Ports
  - Supports CAN Version 2 Parts A and B
- Up to Two Multichannel Audio Serial Ports (McASPs)
  - Transmit and Receive Clocks up to 50 MHz
  - Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
  - Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
  - Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
  - FIFO Buffers for Transmit and Receive (256 Bytes)
- Up to Six UARTs
  - All UARTs Support IrDA and CIR Modes
  - All UARTs Support RTS and CTS Flow Control
  - UART1 Supports Full Modem Control
- Up to Two Master and Slave McSPI Serial Interfaces
  - Up to Two Chip Selects
  - Up to 48 MHz
- Up to Three MMC, SD, SDIO Ports
  - 1-, 4- and 8-Bit MMC, SD, SDIO Modes
  - MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
  - Up to 48-MHz Data Transfer Rate
  - Supports Card Detect and Write Protect
  - Complies With MMC4.3, SD, SDIO 2.0 Specifications
- Up to Three I²C Master and Slave Interfaces
  - Standard Mode (up to 100 kHz)
  - Fast Mode (up to 400 kHz)
- Up to Four Banks of General-Purpose I/O (GPIO) Pins
  - 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
  - GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
- Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
- Eight 32-Bit General-Purpose Timers
  - DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
  - DMTIMER4–DMTIMER7 are Pinned Out
- One Watchdog Timer
- 12-Bit Successive Approximation Register (SAR) ADC
  - 200K Samples per Second
  - Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
- Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
  - Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
  - Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
Device Identification
- Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
  - Production ID
  - Device Part Number (Unique JTAG ID)
  - Device Revision (Readable by Host ARM)
Debug Interface Support
- JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
- Supports Device Boundary Scan
- Supports IEEE 1500
DMA
- On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
  - Transfers to and from On-Chip Memories
  - Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
Inter-Processor Communication (IPC)
- Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
  - Mailbox Registers that Generate Interrupts
    - Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
  - Spinlock has 128 Software-Assigned Lock Registers
Boot Modes
- Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
Package:
- 324-Pin S-PBGA-N324 Package
  (ZCZ Suffix), 0.80-mm Ball Pitch

⁽¹⁾The GFX [SGX530] and LCD modules are not supported for this family of devices, but the "LCD" and "GFX" names are still present in some PLL, power domain, or supply voltage names.

The AMIC110 device is a multiprotocol programmable industrial communications processor providing ready-to-use solutions for most industrial Ethernet and fieldbus communications slaves, as well as some masters. The device is based on the ARM Cortex-A8 processor, peripherals, and industrial interface options. The devices support high-level operating systems (HLOS). Processor SDK Linux^® and TI-RTOS are available free of charge from TI. Other RTOS are also offered by TI ecosystem partners. The AMIC110 microprocessor is an ideal companion communications chip to the C2000 family of microcontrollers for connected drives.

The AMIC110 microprocessor contains the subsystems shown in Figure 1-1 and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor. The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET IRT, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos III, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AMIC110 microprocessor contains the subsystems shown in Figure 1-1 and a brief description of each follows:

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AMIC120

ACTIVE

Sitara processor; Arm Cortex-A9; 10+ Ethernet protocols, encoder protocols AMIC120 includes protocols as AMIC 110 but is a higher performance Cortex - A9 processor with encoder protocols & cryptography

Technical documentation

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	Type	Title	Date
*	Data sheet	AMIC110 Sitara™ SoC datasheet (Rev. D)	12 Dec 2019
*	Errata	AMIC110 Sitara SoC Silicon Errata (Rev. 2.1)	03 Jan 2017
	Application note	Industrial Communication Protocols Supported on Sitara™ Processors (Rev. D)	30 Sep 2021
	Technical article	How to affordably add EtherNet/IP, EtherCAT and PROFINET to an autonomous factory	24 Aug 2020
	White paper	EtherCAT® on Sitara™ Processors (Rev. I)	28 Jul 2020
	White paper	EtherNet/IP on TI's Sitara AM335x Processors (Rev. D)	28 Jul 2020
	E-book	E-book: An engineer’s guide to industrial robot designs	12 Feb 2020
	User guide	AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q)	13 Dec 2019
	Application note	AM335x EMIF Tools	20 Sep 2019
	User guide	Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216	11 Apr 2019
	White paper	Ensuring real-time predictability (Rev. B)	04 Dec 2018
	Technical article	Bringing the next evolution of machine learning to the edge	27 Nov 2018
	Application note	PRU-ICSS EtherCAT Slave Troubleshooting Guide	07 Nov 2018
	White paper	PROFINET on TI’s Sitara™ processors (Rev. D)	13 Oct 2018
	Technical article	How quality assurance on the Processor SDK can improve software scalability	22 Aug 2018
	White paper	An inside look at industrial Ethernet communication protocols (Rev. B)	01 Aug 2018
	User guide	Powering the AM335x With the TPS650250 (Rev. B)	14 Mar 2018
	Technical article	Delivering power to the industrial market with Ethernet	08 Mar 2018
	White paper	Connected sensors in industrial automation (Rev. B)	22 Jun 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TMDXICE110 — AMIC110 Industrial Communications Engine (ICE)

The AMIC110 Industrial Communications Engine (ICE) is a development platform targeted at industrial communications and industrial ethernet in particular. Key to the AMIC110 ICE is the Sitara AMIC110 SoC that features Arm® Cortex™-A8 processor along with the Programmable-Realtime Unit (...)

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User guide

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Evaluation board

CRLNK-3P-SOMS — Critical Link MitySOM system on modules for TI Arm-based Processors

Critical Link is a US-based embedded systems company offering System on Modules (SoMs) and scientific imaging platforms for electronic applications around the world. The MitySOM® and MityDSP® families incorporate DSP, FPGA, and ARM technologies, and are designed for long product lifespan and (...)

From: Critical Link, LLC

Evaluation board

VANWS-3P-VGATEWAY — vGATEWAY reference design from Vanteon Wireless Solutions based on AM335x

Vanteon Gateway™ is a modular bridging platform designed to translate between common wireless interfaces and protocols for Internet of Things (IoT) applications. The Gateway™ platform utilizes the AM335x Sitara ARM-Cortex A8 processor and includes many standard wired and wireless communication (...)

From: Vanteon Wireless Solutions

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Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices. The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2. It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

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Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Software development kit (SDK)

PROCESSOR-SDK-AMIC110 — Processor SDK for AMIC110 Sitara Processors – TI-RTOS Support

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Driver or library

PRU-ICSS-INDUSTRIAL-SW — PRU-ICSS Industrial Software for Sitara™ Processors

The PRU-ICSS Protocols enables real-time industrial communications for TI Sitara processors. The PRU-ICSS protocols are built to use on top of Processor-SDK-RTOS, TI’s unified software development platform, and contain optimized PRU-ICSS firmware, a corresponding PRU-ICSS driver for the (...)

IDE, configuration, compiler or debugger

CCSTUDIO-SITARA — Code Composer Studio (CCS) Integrated Development Environment (IDE) for Sitara ARM Processors

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, (...)

IDE, configuration, compiler or debugger

KUNBUS-3P-INDUSTRIALCOMMS — KUNBUS - A Single Source for Multiprotocol Industrial Communications

KUNBUS is a German-based company specializing in industrial communication. KUNBUS is the ideal partner for industrial communication because KUNBUS offers pre-certified protocol solutions on Sitara™ processors as well as a full suite of additional services to meet the customer's needs.

Common (...)

From: KUNBUS

Software programming tool

UNIFLASH — UniFlash stand-alone flash tool for microcontrollers, Sitara™; processors and SimpleLink™

Supported devices: CC13xx, CC25xx, CC26xx, CC3x20, CC3x30, CC3x35, Tiva, C2000, MSP43x, Hercules, PGA9xx, IWR12xx, IWR14xx, IWR16xx, IWR18xx , IWR68xx, AWR12xx, AWR14xx, AWR16xx, AWR18xx. Command line only: AM335x, AM437x, AM571x, AM572x, AM574x, AM65XX, K2G

CCS Uniflash is a standalone tool used (...)