SLASE67A January 2015 – August 2019 ADS54J54
PRODUCTION DATA.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | CLK SEL CD | CLK DIV CD | 0 | CLK PHASE SELECT CD | SYSREF SEL CD | CLK SEL AB | CLK DIV AB | 0 | CLK PHASE SELECT AB |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D14 | CLK SEL CD | R/W | 1 | Clock source selection for channel C and D
0 = Channel CD clock output divider 1 = Channel AB clock output divider (default) |
D13:D12 | CLK DIV CD | R/W | 00 | Channel CD clock divider setting
00 = Clock input is up to 500 MHz. Input clock is not divided (default) 01 = /2 10 = /4 11 = Not used |
D10:D8 | CLK PHASE SELECT CD | R/W | 000 | Selects phase of channel divided clock, but depends on clock divider setting. When clock CD divider is set to:
/1 = 2 phases are available (0º or 180º) /2 = 4 phases are available (0º, 90º, 180º or 270º) /4 = 8 phases are available (0º, 45º, 90º, 135º, 180º, 225º, 270º or 315º) When switching clock phases, register 0x08, D9 must be enabled first and then disabled after the switch to ensure glitch-free operation. |
D7 | SYSREF SEL CD | R/W | 0 | SYSREF Input selection for channel C and D
0 = Use SYSREFAB inputs (default) 1 = Use SYSREFCD inputs |
D6 | CLK SEL AB | R/W | 1 | Clock source selection for channel A and B
0 = Channel CD clock output divider 1 = Channel AB clock output divider (default) |
D5:D4 | CLK DIV AB | R/W | 00 | Channel AB clock divider setting
00 = Clock input is up to 500 MHz. Input clock is not divided (default) 01 = /2 10 = /4 11 = Not used |
D2:D0 | CLK PHASE SELECT AB | R/W | 000 | Selects phase of channel AB divided clock, but depends on clock divider setting. When clock divider is set to:
/1 = 2 phases are available (0º or 180º) /2 = 4 phases are available (0º, 90º, 180º or 270º) /4 = 8 phases are available (0º, 45º, 90º, 135º, 180º, 225º, 270º or 315º) When switching clock phases, register 0x07, D9 must be enabled first and then disabled after the switch to ensure glitch-free operation. |