SNAS783C June   2020  – February 2021 LMX2820

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Input Path
        1. 7.3.2.1 Input Path Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Programmable Input Multiplier (MULT)
        4. 7.3.2.4 R Divider (PLL_R)
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
        1. 7.3.4.1 Integer N Divide Portion (PLL_N)
        2. 7.3.4.2 Fractional N Divide Portion (PLL_NUM and PLL_DEN)
        3. 7.3.4.3 Modulator Order (MASH_ORDER)
      5. 7.3.5  LD Pin Lock Detect
      6. 7.3.6  MUXOUT Pin and Readback
      7. 7.3.7  Internal VCO
        1. 7.3.7.1 VCO Calibration
          1. 7.3.7.1.1 Determining the VCO Gain and Ranges
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Frequency Doubler
      10. 7.3.10 Output Buffer
      11. 7.3.11 Power-Down Modes
      12. 7.3.12 Phase Synchronization for Multiple Devices
        1. 7.3.12.1 SYNC Categories
        2. 7.3.12.2 Phase Adjust
          1. 7.3.12.2.1 Using MASH_SEED to Create a Phase Shift
          2. 7.3.12.2.2 Static vs. Dynamic Phase Adjust
          3. 7.3.12.2.3 Fine Adjustments to Phase Adjust
      13. 7.3.13 SYSREF
      14. 7.3.14 Fast VCO Calibration
      15. 7.3.15 Double Buffering (Shadow Registers)
      16. 7.3.16 Output Mute Pin and Ping Pong Approaches
    4. 7.4 Device Functional Modes
      1. 7.4.1 External VCO Mode
      2. 7.4.2 External Feedback Input Pins
        1. 7.4.2.1 PFDIN External Feedback Mode
        2. 7.4.2.2 RFIN External Feedback Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Treatment of Unused Pins
      2. 8.1.2 External Loop Filter
      3. 8.1.3 Using Instant Calibration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Initialization and Power-on Sequencing
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The LMX2820 is a high-performance, wideband frequency synthesizer with an integrated VCO and output divider. The VCO operates from 5.65 GHz to 11.3 GHz, and this can be combined with the output divider and doubler to produce any frequency in the range of 45 MHz to 22.6 GHz. Within the input path, there are two dividers and a multiplier for flexible frequency planning. The multiplier also allows the reduction of spurs by moving the frequencies away from the integer boundary. The PLL is fractional-N PLL with a programmable delta-sigma modulator up to third order. The fractional denominator is a programmable 32-bit long, which can easily provide fine frequency steps below 1-Hz resolution, or be used to do exact fractions like 1/3, 7/1000, and many others. The phase frequency detector goes up to 300 MHz in fractional mode or 400 MHz in integer mode, although minimum N-divider values must also be taken into account. For applications where deterministic or adjustable phase is desired, the PSYNC Pin can be used to get the phase relationship between the OSCIN and RFOUT pins deterministic. When this is done, the phase can be adjusted in very fine steps of the VCO period divided by the fractional denominator. The ultra-fast VCO calibration is designed for applications where the frequency must be swept or abruptly changed. The JESD204B support includes using the SROUT output to create a differential SYSREF output that can be either a single pulse or a series of pulses that occur at a programmable distance away from the rising edges of the output signal. The LMX2820 device requires only a single 3.3-V power supply. The internal power supplies are provided by integrated LDOs, eliminating the need for high-performance external LDOs. The digital logic for the SPI interface and is compatible with voltage levels from 1.8 V to 3.3 V. Table 7-1 shows the range of several of the dividers, multipliers, and fractional settings.

Table 7-1 Dividers, Multipliers, and Fractional Settings
BLOCKSUB-BLOCKFIELDMINMAXCOMMENTS
Input PathDoublerOSC_2X0
(= 1X)		1 (= 2X)The low noise doubler can be used to increase the phase detector frequency to improve phase noise and avoid spurs.
Pre-R DividerPLL_R_PRE14095Only use the Pre-R divider if the frequency is too high for the input multiplier or for the Post-R divider.
Input MultiplierMULT37The input multiplier is effective for spur avoidance, increases PLL noise.
Post-R DividerPLL_R1255The maximum input frequency for this divider is 500 MHz for PLLR=2 and 250 MHz for PLL_R>2. Use the Pre-R divider if necessary.
N DividerN DividerPLL_N≥ 1232767The minimum divide depends on the modulator order, VCO frequency/core, and choice of internal/external VCO.
Fractional numeratorPLL_NUM1232 – 1 = 4294967295PLL_NUM should be smaller than PLL_DEN
Fractional DenominatorPLL_DEN0232 – 1 = 4294967295The fractional denominator is programmable and can assume any value between 1 and 232 – 1; it is not a fixed denominator.
Fractional OrderMASH_ORDER03The fractional order is programmable from 0 to 3; 0 is integer mode.
PFDIN PathPFD Input DividerEXTPFD_DIV163
External VCOExternal VCO DividerEXTVCO_DIV12If the VCO frequency exceeds 11.3 GHz, then use divide by 2, otherwise use divide by 1 (bypass).
SYSREFPre-DividerSYSREF_DIV_PRE14Supports 1, 2 and 4 ONLY. There is an additional divide-by-2 in this block. The total pre-divider value is 2 × SYSREF_DIV_PRE.
DividerSYSREF_DIV02047Total divider value is 2 + SYSREF_DIV.
Extra DivideNone44This is a fixed divide-by-4 divider.
OutputsOUTA DividerCHDIVA2128This is a power-of-2 divider that supports 2, 4, 8, 16, 32, 64 and 128.
OUTB DividerCHDIVB2128This is a power-of-2 divider that supports 2, 4, 8, 16, 32, 64 and 128.
Output Frequencyn/a4522600Below 5.65 GHz, the channel divider is used. 5.65 - 11.23 GHz is direct VCO. 11.3 - 22.6 GHz is using the output doubler.