SNAS783C June   2020  – February 2021 LMX2820

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Input Path
        1. 7.3.2.1 Input Path Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Programmable Input Multiplier (MULT)
        4. 7.3.2.4 R Divider (PLL_R)
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
        1. 7.3.4.1 Integer N Divide Portion (PLL_N)
        2. 7.3.4.2 Fractional N Divide Portion (PLL_NUM and PLL_DEN)
        3. 7.3.4.3 Modulator Order (MASH_ORDER)
      5. 7.3.5  LD Pin Lock Detect
      6. 7.3.6  MUXOUT Pin and Readback
      7. 7.3.7  Internal VCO
        1. 7.3.7.1 VCO Calibration
          1. 7.3.7.1.1 Determining the VCO Gain and Ranges
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Frequency Doubler
      10. 7.3.10 Output Buffer
      11. 7.3.11 Power-Down Modes
      12. 7.3.12 Phase Synchronization for Multiple Devices
        1. 7.3.12.1 SYNC Categories
        2. 7.3.12.2 Phase Adjust
          1. 7.3.12.2.1 Using MASH_SEED to Create a Phase Shift
          2. 7.3.12.2.2 Static vs. Dynamic Phase Adjust
          3. 7.3.12.2.3 Fine Adjustments to Phase Adjust
      13. 7.3.13 SYSREF
      14. 7.3.14 Fast VCO Calibration
      15. 7.3.15 Double Buffering (Shadow Registers)
      16. 7.3.16 Output Mute Pin and Ping Pong Approaches
    4. 7.4 Device Functional Modes
      1. 7.4.1 External VCO Mode
      2. 7.4.2 External Feedback Input Pins
        1. 7.4.2.1 PFDIN External Feedback Mode
        2. 7.4.2.2 RFIN External Feedback Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Treatment of Unused Pins
      2. 8.1.2 External Loop Filter
      3. 8.1.3 Using Instant Calibration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Initialization and Power-on Sequencing
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-4BAE681E-3339-4B06-B6FC-77B199EFEB90-low.gif Figure 5-1 RTC Package48-Pin VQFNTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.(1)
SUPPLY AND GROUND
VCCBUF 24 P Output buffer supply. Connect to 3.3-V with a low-ESR, 0.1-µF and a 1-µF decoupling capacitor to ground.
VCCBUF2 33 P Buffer supply. Connect to 3.3-V with a low-ESR, 0.1-µF and a 1-µF decoupling capacitor to ground.
VCCCP 13 P Charge pump supply. Connect to 3.3-V with a 1-µF decoupling capacitor to ground.
VCCDIG 7 P Digital supply. Connect to 3.3-V with a low-ESR, 0.1-µF and a 1-µF decoupling capacitor to ground.
VCCMASH 17 P Digital supply. Connect to 3.3-V with a low-ESR, 0.1-µF and a 1-µF decoupling capacitor to ground.
VCCVCO 45 P VCO supply. Connect to 3.3-V with a low-ESR, 0.1-µF and a 1-µF decoupling capacitor to ground.
GND 2 G Ground
4
6
15
16
27
29
32
40
42
47
48
DAP — — Connect the GND pin to the exposed thermal pad for correct operation. Connect the thermal pad to any internal PCB ground plane using multiple vias for good thermal performance.
NC 35 NC Connect to ground.
BIAS/LDO BYPASS
BIASVAR 41 B VCO varactor bias. Connect a 1-µF decoupling capacitor to ground.
BIASVCO 3 B VCO bias. Connect a low-ESR capacitor in the range of 0.47-µF (for fastest calibration time) to 4.7-µF (for optimal in-band phase noise)
BIASVCO2 34 B VCO bias. Connect a 1-µF decoupling capacitor to ground. Place close to pin.
REFVCO2 36 B VCO supply reference. Connect a 1-µF decoupling capacitor to ground.
REGIN 10 B Input reference path regulator decoupling. Connect a 1-µF decoupling capacitor to ground. Place close to pin. An additional low-ESR, 0.1-µF decoupling capacitor is recommended for high-frequency noise filtering.
REGVCO 46 B VCO regulator node. Connect a 1-µF decoupling capacitor to ground.
REFVCO 44 B VCO supply reference. Connect a 10-µF decoupling capacitor to ground.
DIGITAL INPUTS
CE 1 I Chip Enable. High-impedance CMOS input. 1.8-V to 3.3-V logic. Active HIGH powers on the device.
MUTE 37 I Buffer mute control. High-impedance CMOS input. 1.8-V to 3.3-V logic.
PSYNC 5 I Phase synchronization with configurable input signal level. Connect with series 100 Ω to PSYNC signal, or to GND if not used.
CS# 39 I SPI latch. High-impedance CMOS input. 1.8-V to 3.3-V logic.
SCK 18 I SPI clock. High-impedance CMOS input. 1.8-V to 3.3-V logic.
SDI 19 I SPI data. High-impedance CMOS input. 1.8-V to 3.3-V logic.
ANALOG INPUTS
OSCIN_P 8 I Reference input clock (+). High impedance self-biasing pin. Requires AC coupling. If not being used, AC-couple it to ground through a 50-Ω resistor.
PFDIN 20 I External PFD input. Self-biasing pin. Requires AC coupling and an external 50-Ω resistor to ground.
RFIN 28 I External VCO input. Internal 50 Ω terminated. Requires AC coupling.
OSCIN_N 9 I Reference input clock (–). High impedance self-biasing pin. Requires AC coupling. If not being used, AC-couple it to ground through a 50-Ω resistor.
SRREQ_P 11 I Differential SYSREF input clock (+). Supports AC and DC coupling.
VTUNE 43 I VCO tuning voltage input. Connect a 1.5-nF or more capacitor to VCO ground.
SRREQ_N 12 I Differential SYSREF input clock (–). Supports AC and DC coupling.
OUTPUTS
CPOUT 14 O Charge pump output. Recommend connecting C1 of loop filter close to this pin.
LD 38 O Lock detect output. 3.3-V logic.
MUXOUT 23 O SPI readback output. 3.3-V logic. High impedance when CE = LOW.
RFOUTA_N 30 O, PU Differential output A (–). Internal 50-Ω pullup. Requires AC coupling.
RFOUTA_P 31 O, PU Differential output A (+). Internal 50-Ω pullup. Requires AC coupling.
RFOUTB_N 25 O, PU Differential output B (–). Internal 50-Ω pullup. Requires AC coupling.
RFOUTB_P 26 O, PU Differential output B (+). Internal 50-Ω pullup. Requires AC coupling.
SROUT_N 22 O, PU Differential SYSREF output (–). Internal 50-Ω pullup.
SROUT_P 21 O, PU Differential SYSREF output (+). Internal 50-Ω pullup.
(1) The definitions below define the I/O type for each pin.
  • P = Power supply
  • G = Ground
  • NC = No connect. Pin may be grounded or left unconnected.
  • B = Bias/LDO Bypass
  • I = Input
  • O = Output
  • PU = Pullup