SNAS783C June   2020  – February 2021 LMX2820

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Input Path
        1. 7.3.2.1 Input Path Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Programmable Input Multiplier (MULT)
        4. 7.3.2.4 R Divider (PLL_R)
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
        1. 7.3.4.1 Integer N Divide Portion (PLL_N)
        2. 7.3.4.2 Fractional N Divide Portion (PLL_NUM and PLL_DEN)
        3. 7.3.4.3 Modulator Order (MASH_ORDER)
      5. 7.3.5  LD Pin Lock Detect
      6. 7.3.6  MUXOUT Pin and Readback
      7. 7.3.7  Internal VCO
        1. 7.3.7.1 VCO Calibration
          1. 7.3.7.1.1 Determining the VCO Gain and Ranges
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Frequency Doubler
      10. 7.3.10 Output Buffer
      11. 7.3.11 Power-Down Modes
      12. 7.3.12 Phase Synchronization for Multiple Devices
        1. 7.3.12.1 SYNC Categories
        2. 7.3.12.2 Phase Adjust
          1. 7.3.12.2.1 Using MASH_SEED to Create a Phase Shift
          2. 7.3.12.2.2 Static vs. Dynamic Phase Adjust
          3. 7.3.12.2.3 Fine Adjustments to Phase Adjust
      13. 7.3.13 SYSREF
      14. 7.3.14 Fast VCO Calibration
      15. 7.3.15 Double Buffering (Shadow Registers)
      16. 7.3.16 Output Mute Pin and Ping Pong Approaches
    4. 7.4 Device Functional Modes
      1. 7.4.1 External VCO Mode
      2. 7.4.2 External Feedback Input Pins
        1. 7.4.2.1 PFDIN External Feedback Mode
        2. 7.4.2.2 RFIN External Feedback Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Treatment of Unused Pins
      2. 8.1.2 External Loop Filter
      3. 8.1.3 Using Instant Calibration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Initialization and Power-on Sequencing
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Typical Characteristics

GUID-5011543C-9EEB-483B-8FA2-94508743D8CC-low.gif
fOUT = 6 GHz, fPD=200 MHz,Jitter=36 fs 12k-20 MHz
Figure 6-1 Closed-Loop Noise
GUID-20201113-CA0I-Z5HK-MRQZ-GLNG2TTP8Z2X-low.gif

 

Figure 6-3 Noise Floor
GUID-20201106-CA0I-HDBF-H4X2-ZP6XBHJB6WBH-low.gifFigure 6-5 PLL Noise Metric Degradation vs. OSCin Slew Rate
GUID-20201106-CA0I-LG0R-MS5Z-XTCNMTGWQ7HS-low.gif
Single-ended, OUTx_PWR=7, board losses de-embedded
Figure 6-7 Output Power vs. Temperature
GUID-3C1A13BF-D6E2-4FC6-AB0F-EB619E0783CC-low.gifFigure 6-9 Output Half Harmonic with Doubler Enabled
GUID-20201105-CA0I-WX1Z-LZLS-2QDVH2FXCV5M-low.gifFigure 6-11 PFDIN Pin Input Sensitivity
GUID-20201105-CA0I-XXDC-FGH3-TLKPV8CC0NJ8-low.gifFigure 6-13 RFIN Input Sensitivity
GUID-20201113-CA0I-2TXZ-LWH5-53DGDJP6VFB0-low.gif
Approximation = 0.85*rb_TEMP_SENS - 415
Figure 6-15 Temperature Sensor Readback
GUID-20201113-CA0I-KGZJ-1LXN-QXZKCX0TQ5NV-low.gif
This is showing the output is muted in well under 200 ns
Figure 6-17 Mute Pin Disable Output Time
GUID-DBE1D129-5644-48B4-905C-D1CED170A4E1-low.gif
Integration Range is 12k-20 MHz
Figure 6-2 Integrated Jitter
GUID-20201105-CA0I-BSTP-RVWN-PM38BCZ5VPGF-low.gif
fOSC=100 MHz, fPD=200 MHz, fOUT=6 GHz, OSC_2X=1
Use of input doubler slightly degrades PLL noise metrics.
Figure 6-4 PLL Noise Metrics
GUID-20201106-CA0I-0NRM-ZKMW-VDP0PVBL4ZXS-low.gifFigure 6-6 IPLL Noise Metric Degradation vs. Charge Pump Gain
GUID-20201106-CA0I-GJTX-RCQC-BK3VV19GZK8W-low.gifFigure 6-8 Output Power vs. OUTx_PWR
GUID-20201110-CA0I-VDBK-5HXD-FFDQFXJPJ27P-low.gifFigure 6-10 RF Output Return Loss
GUID-20201105-CA0I-L36Z-MDT7-TW3TNN9H9WTD-low.gifFigure 6-12 OSCin Input Sensitivity
GUID-20201110-CA0I-BTGQ-JHTF-MCCV2M6X1THN-low.gifFigure 6-14 RFIN Return Loss
GUID-20201113-CA0I-4JWC-STB4-D1W9ZRWX79KH-low.gif
fVCO=8.4 GHz, SYSREF_DIV_PRE=8,Step Size=7.6 ps
Figure 6-16 SysRef Delays vs Temperature
GUID-20201113-CA0I-SZV4-JKJH-SMQMFRNS4CVS-low.gif
Output is unmuted in under 200 μs. DC bias level can stabilize faster if smaller AC-coupling capacitor is used.
Figure 6-18 Mute Pin Enable Output Time