In general, the layout guidelines are similar to most other PLL devices. Here are some specific guidelines.
- GND pins may be routed on the package back to the DAP.
- The OSCIN pins, these are internally biased and must be AC coupled.
- If not used, the SRREQ pins may be grounded to the DAP.
- For optimal VCO phase noise in the 200 kHz to 1 MHz range, it is ideal that the capacitor closest to the VTUNE pin be at least 1.5 nF. As requiring this larger capacitor may restrict the loop bandwidth, this value can be reduced (to say 1 nF) at the expense of VCO phase noise.
- If a single-ended output is needed, the other side must have the same loading. However, the routing for the used side can be optimized by routing the complementary side through a via to the other side of the board. On this side, make the load look equivalent to the side that is used.
- Ensure DAP on device is well-grounded with many vias, preferably copper filled.
- Have a thermal pad that is as large as the LMX2820 exposed pad. Add vias to the thermal pad to maximize thermal performance.
- Use a low loss dielectric material, such as Rogers 4350B, for optimal output power.