Layout is very important to maximize the electrical and thermal performance of the total system. General guidelines are provided, but the form factor, board stack-up, and proximity of other components also need to be considered to maximize the performance.

1. VBUS and VOUT traces should be as short and wide as possible to accommodate for high current.
2. Copper trace of VBUS and VOUT should run at least 150 mil (3.81 mm) straight (perpendicular to WCSP ball array) before making turns.
3. CFLY caps should be placed as close as possible to the device and CFLY trace should be as wide as possible until close to the IC.
4. CLFY pours should be as symmetrical between CFH pads and CFL pads as possible.
5. Place low ESR bypass capacitors to ground for VBUS, PMID, and VOUT. The capacitor should be placed as close to the device pins as possible.
6. The CFLY pads should be as small as possible, and the CFLY caps placed as close as possible to the device, as these are switching pins and this will help reduce EMI.
7. Do not route so the power planes are interrupted by signal traces.

Refer to the EVM design and more information in the BQ25960EVM (BMS041) Evaluation Module User's Guide for the recommended component placement with trace and via locations.