JAJSHI5G august   2012  – april 2023 DLP7000

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  LVDS Timing Requirements
    8. 7.8  LVDS Waveform Requirements
    9. 7.9  Serial Control Bus Timing Requirements
    10. 7.10 Systems Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Window Characteristics
    14. 7.14 Chipset Component Usage Specification
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Chipset DMD Features
        1. 8.3.1.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
        2. 8.3.1.2 DLPA200 - DMD Micromirror Driver
        3. 8.3.1.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
        4. 8.3.1.4 DLP7000 - DLP 0.7 XGA 2xLVDS Type-A DMD
          1. 8.3.1.4.1 DLP7000 XGA Chip Set Interfaces
            1. 8.3.1.4.1.1 DLPC410 Interface Description
              1. 8.3.1.4.1.1.1 DLPC410 IO
              2. 8.3.1.4.1.1.2 Initialization
              3. 8.3.1.4.1.1.3 DMD Device Detection
              4. 8.3.1.4.1.1.4 Power Down
          2. 8.3.1.4.2 DLPC410 to DMD Interface
            1. 8.3.1.4.2.1 DLPC410 to DMD IO Description
            2. 8.3.1.4.2.2 Data Flow
          3. 8.3.1.4.3 DLPC410 to DLPA200 Interface
            1. 8.3.1.4.3.1 DLPA200 Operation
            2. 8.3.1.4.3.2 DLPC410 to DLPA200 IO Description
          4. 8.3.1.4.4 DLPA200 to DLP7000 Interface
            1. 8.3.1.4.4.1 DLPA200 to DLP7000 Interface Overview
        5. 8.3.1.5 Measurement Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 DMD Operation
        1. 8.4.1.1 Single Block Mode
        2. 8.4.1.2 Dual Block Mode
        3. 8.4.1.3 Quad Block Mode
        4. 8.4.1.4 Global Mode
    5. 8.5 Optical Interface and System Image Quality Considerations
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation - Lumens Based (typically used for display applications)
      4. 8.6.4 Micromirror Array Temperature Calculation - Power Density Based
      5. 8.6.5 62
    7. 8.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Device Description
      3. 9.2.3 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 DMD Interface
        1. 11.1.3.1 Trace Length Matching
      4. 11.1.4 DLP7000 Decoupling
        1. 11.1.4.1 Decoupling Capacitors
      5. 11.1.5 VCC and VCC2
      6. 11.1.6 DMD Layout
      7. 11.1.7 DLPA200
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1  Device Support
      1. 12.1.1 Device Marking
    2. 12.2  サード・パーティ製品に関する免責事項
    3. 12.3  Documentation Support
      1. 12.3.1 Related Documents
    4. 12.4  ドキュメントの更新通知を受け取る方法
    5. 12.5  サポート・リソース
    6. 12.6  静電気放電に関する注意事項
    7. 12.7  Export Control Notice
    8. 12.8  用語集
    9. 12.9  Related Links
    10. 12.10 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報
DLPC410 IO

Table 8-2 describes the inputs and outputs of the DLPC410 to the user. For more details on these signals, see the DLPC410 data sheet (DLPS024).

Table 8-2 Input/Output Description
PIN NAMEDESCRIPTIONI/O
ARSTAsynchronous active low resetI
CLKIN_RReference clock, 50 MHzI
DIN_[A,B,C,D](15:0)LVDS DDR input for data bus A,B,C,D (15:0)I
DCLKIN[A,B,C,D]LVDS inputs for data clock (200 - 400 MHz) on bus A, B, C, and DI
DVALID[A,B,C,D]LVDS input used to start write sequence for bus A, B, C, and DI
ROWMD(1:0)DMD row address and row counter controlI
ROWAD(10:0)DMD row address pointerI
BLK_AD(3:0)DMD mirror block address pointerI
BLK_MD(1:0)DMD mirror block reset and clear command modesI
PWR_FLOATUsed to float DMD mirrors before complete loss of powerI
DMD_TYPE(3:0)DMD type in useO
RST_ACTIVEIndicates DMD mirror reset in progressO
INIT_ACTIVEInitialization in progress.O
VLED0System “heartbeat” signalO
VLED1Denotes initialization completeO