Optically, the DLP7000 consists of 786,432 highly reflective, digitally switchable, micrometer-sized mirrors (“micromirrors”), organized in a two-dimensional array of 1024 micromirror columns by 768 micromirror rows (Figure 8-4). Each aluminum micromirror is approximately 13.68 microns in size (see the “Micromirror Pitch” in Figure 8-4), and is switchable between two discrete angular positions: –12° and +12°. The angular positions are measured relative to a 0° “flat state”, which is parallel to the array plane (see Figure 8-5). The tilt direction is perpendicular to the hinge-axis which is positioned diagonally relative to the overall array. The “On State” landed position is directed towards “Row 0, Column 0” (upper left) corner of the device package (see the “Micromirror Hinge-Axis Orientation” in Figure 8-4). In the field of visual displays, the 1024 by 768 “pixel” resolution is referred to as "XGA".

Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the micromirror "clocking pulse" is applied. The angular position (–12° or +12°) of the individual micromirrors changes synchronously with a micromirror “clocking pulse”, rather than being synchronous with the CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a micromirror "clocking pulse" will result in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a memory cell followed by a micromirror "clocking pulse" will result in the corresponding micromirror switching to a –12° position.

Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the CMOS memory. Second, application of a Micromirror Clocking Pulse to all or a portion of the micromirror array (depending upon the configuration of the system). Micromirror Clocking Pulses are generated externally by a DLPA200, with application of the pulses being coordinated by the DLPC410 controller.

Around the perimeter of the 1024 by 768 array of micromirrors is a uniform band of “border” micromirrors. The border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each side of the 1024 by 768 active array.

Figure 8-1 shows a DLPC410 and DLP7000 Chipset Block Diagram. The DLPC410 and DLPA200 control and coordinate the data loading and micromirror switching for reliable DLP7000 operation. The DLPR410 is the programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset components, see Application and Implementation. For a typical system application using the DLPC410 chipset including the DLP7000, see Figure 9-1.