JAJSHI5G august 2012 – april 2023 DLP7000
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fDCLK_* | DCLK_* clock frequency {where * = [A, or B]} | 200 | 400 | MHz | |
tc | Clock Cycle - DLCK_* | 2.5 | ns | ||
tw | Pulse Width - DLCK_* | 1.25 | ns | ||
ts | Setup Time - D_*[15:0] and SCTRL_* before DCLK_* | 0.35 | ns | ||
th | Hold Time, D_*[15:0] and SCTRL_* after DCLK_* | 0.35 | ns | ||
tskew | Skew between bus A and B | –1.25 | 1.25 | ns |