SLVSD29 October   2015 DRV8704

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Motor Drivers
      2. 7.3.2  Direct PWM Input Mode (Dual Brushed DC Gate Driver)
      3. 7.3.3  Current Regulation
      4. 7.3.4  Decay Modes
      5. 7.3.5  Blanking Time
      6. 7.3.6  Gate Drivers
      7. 7.3.7  Configuring Gate Drivers
      8. 7.3.8  External FET Selection
      9. 7.3.9  Protection Circuits
        1. 7.3.9.1 Overcurrent Protection (OCP)
        2. 7.3.9.2 Gate Driver Fault (PDF)
        3. 7.3.9.3 Thermal Shutdown (TSD)
        4. 7.3.9.4 Undervoltage Lockout (UVLO)
      10. 7.3.10 Serial Data Format
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 Control Registers
        1. 7.5.1.1 CTRL Register (Address = 0x00h)
          1. Table 4. CTRL Register
        2. 7.5.1.2 TORQUE Register (Address = 0x01h)
          1. Table 5. TORQUE Register
        3. 7.5.1.3 OFF Register (Address = 0x02h)
          1. Table 6. OFF Register
        4. 7.5.1.4 BLANK Register (Address = 0x03h)
          1. Table 7. BLANK Register
        5. 7.5.1.5 DECAY Register (Address = 0x04h)
          1. Table 8. DECAY Register
        6. 7.5.1.6 Reserved Register Address = 0x05h
          1. Table 9. Reserved Register
        7. 7.5.1.7 DRIVE Register Address = 0x06h
          1. Table 10. DRIVE Register
        8. 7.5.1.8 STATUS Register (Address = 0x07h)
          1. Table 11. STATUS Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 Current Chopping Configuration
        4. 8.2.2.4 Decay Modes
        5. 8.2.2.5 Sense Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DCP Package
38-Pin HTSSOP
Top View
DRV8704 po_lvsd29.gif

Pin Functions

PIN (1) TYPE DESCRIPTION
NAME NO.
POWER AND GROUND
CP1 1 IO Charge pump flying capacitor Connect a 0.1-μF X7R capacitor between CP1 and CP2. Voltage rating must be greater than applied VM voltage.
CP2 2 IO Charge pump flying capacitor
GND 5, 19, 29, 38, PPAD — Device ground All pins must be connected to ground
RSVD 20 — Reserved Leave this pin disconnected
V5 6 O 5-V regulator output 5-V linear regulator output. Bypass to GND with a 0.1-μF 10-V X7R ceramic capacitor.
VCP 3 IO High-side gate drive voltage Connect a 1-μF 16-V X7R ceramic capacitor to VM
VINT 7 — Internal logic supply voltage Logic supply voltage. Bypass to GND with a 1-μF 6.3-V X7R ceramic capacitor.
VM 4 — Motor power supply Connect to motor supply voltage. Bypass to GND with a 0.1-μF ceramic capacitor plus a 100-μF electrolytic capacitor.
CONTROL
AIN1 10 I Bridge A IN1 Controls bridge A OUT1. Internal pulldown.
AIN2 11 I Bridge A IN2 Controls bridge A OUT2. Internal pulldown.
BIN1 12 I Bridge B IN1 Controls bridge B OUT1. Internal pulldown.
BIN2 13 I Bridge B IN2 Controls bridge B OUT2. Internal pulldown.
RESET 9 I Reset input Active-high reset input initializes all internal logic and disables the H-bridge outputs. Internal pulldown.
SLEEPn 8 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown.
SERIAL INTERFACE
SCLK 14 I Serial clock input Rising edge clocks data into part for write operations. Falling edge clocks data out of part for read operations. Internal pulldown.
SCS 16 I Serial chip select input Active high to enable serial data transfer. Internal pulldown.
SDATI 15 I Serial data input Serial data input from controller. Internal pulldown.
SDATO 17 O Serial data output Serial data output to controller. Open-drain output requires external pull-up.
STATUS
FAULTn 18 OD Fault Logic low when in fault condition. Open-drain output requires external pullup.
OUTPUT
A1HS 36 O Bridge A out 1 HS gate Bridge A out 1 HS FET gate
A1LS 35 O Bridge A out 1 LS gate Bridge A out 1 LS FET gate
A2HS 31 O Bridge A out 2 HS gate Bridge A out 2 HS FET gate
A2LS 32 O Bridge A out 2 LS gate Bridge A out 2 LS FET gate
AISENN 33 I Bridge A Isense – in Ground at sense resistor for bridge A
AISENP 34 I Bridge A Isense + in Current sense resistor for bridge A
AOUT1 37 I Bridge A output 1 Output node of bridge A out 1
AOUT2 30 I Bridge A output 2 Output node of bridge A out 2
B1HS 27 O Bridge B out 1 HS gate Bridge B out 1 HS FET gate
B1LS 26 O Bridge B out 1 LS gate Bridge B out 1 LS FET gate
B2HS 22 O Bridge B out 2 HS gate Bridge B out 2 HS FET gate
B2LS 23 O Bridge B out 2 LS gate Bridge B out 2 LS FET gate
BISENN 24 I Bridge B Isense – in Ground at sense resistor for bridge B
BISENP 25 I Bridge B Isense + in Current sense resistor for bridge B
BOUT1 28 I Bridge B output 1 Output node of bridge B out 1
BOUT2 21 I Bridge B output 2 Output node of bridge B out 2
(1) Directions: I = Input, O = Output, OZ = Tri-state output, OD = Open-drain output, IO = Input/output