SLUUCU7 November   2023 BQ25960H

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Equipment
    2. 2.2 Equipment Setup
    3. 2.3 I/O Descriptions
  9. 3Software
    1. 3.1 Software Setup
  10. 4Implementation Results
    1. 4.1 Test Procedure
      1. 4.1.1 Initial Settings
      2. 4.1.2 Communication Verification
      3. 4.1.3 Switched Cap Mode Charge Verification
      4. 4.1.4 Bypass Mode Charge Verification
      5. 4.1.5 Dual BQ25960H Operation
      6. 4.1.6 BQ25611D Charge Verification
  11. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout Guidelines
      1. 5.2.1 Board Layout
    3. 5.3 Bill of Materials
  12. 6Additional Information
    1.     Trademarks

4.1.5 Dual BQ25960H Operation

The BQ25960H EVM also supports dual BQ25960H operation, with U1 operating as the primary charger, and U2 operating as the secondary charger. This allows each BQ25960H to operate at a lower charging current with higher efficiency compared with a single BQ25960H operating at the same total charging current. As a reminder, if the jumper settings in Table 3-2 have been followed, then the I2C address for U1 is 0x65, and the I2C address for U2 is 0x67. Note that the jumper settings for JP3 and JP9 are different for single BQ25960H and dual BQ25960H operation.

  1. For U1, follow the previous steps to enable charge in either switched cap mode or bypass mode. U1 begins charging.
  2. Select I2C address 0x67 to communicate with U2.
  3. Follow the same steps to enable charge for U2. The two BQ25960H devices are now charging in parallel.