SLWU087E november   2013  – june 2023

 

  1.   1
  2.   High Speed Data Converter Pro GUI
  3.   Trademarks
  4. 1 Introduction
  5. 2 Software Start up
    1. 2.1 Installation Instructions
    2. 2.2 USB Interface and Drivers
    3. 2.3 Device ini Files
  6. 3 User Interface
    1. 3.1 Toolbar
      1. 3.1.1 File Options
        1. 3.1.1.1 User Profiles
        2. 3.1.1.2 Resize Window
      2. 3.1.2 Instrument Options
        1. 3.1.2.1 TSW14J56 and High Speed Data Converter (HSDC) Pro Eye Quality Analysis
        2. 3.1.2.2 IO Delay
        3. 3.1.2.3 JESD204B Error Injection
        4. 3.1.2.4 FPGA Registers Write Read
      3. 3.1.3 Data Capture Option
        1. 3.1.3.1 Capture Option
        2. 3.1.3.2 Trigger Option
        3. 3.1.3.3 Using Multiple TSW14xxx and ADC EVM’s for Simultaneous Capture using Trigger Option
          1. 3.1.3.3.1 Hardware Setup
          2. 3.1.3.3.2 Setting up the Slave Board
          3. 3.1.3.3.3 Setting up the Master Board
          4. 3.1.3.3.4 Read Captured Memory from the Slave Board
      4. 3.1.4 Test Options
        1. 3.1.4.1  Notch Frequency Bins
        2. 3.1.4.2  2 Channel Display and Cursor Lock
        3. 3.1.4.3  Analysis Window Markers
        4. 3.1.4.4  X-Scale in Time
        5. 3.1.4.5  Y-Scale in Voltage
        6. 3.1.4.6  Other Frequency Options
        7. 3.1.4.7  NSD Marker
        8. 3.1.4.8  Phase Plot
        9. 3.1.4.9  Phase in Degree
        10. 3.1.4.10 Histogram
        11. 3.1.4.11 Disable User Popups
        12. 3.1.4.12 HSDC Pro Lite Version
      5. 3.1.5 Help
    2. 3.2 Status Windows
    3. 3.3 Mode Selection
    4. 3.4 Device Selection
    5. 3.5 Skip Configuration
    6. 3.6 Capture Button (ADC Mode Only)
    7. 3.7 Test Selection (ADC Mode only)
      1. 3.7.1 Single Tone FFT
        1. 3.7.1.1 Parameter Controls
        2. 3.7.1.2 ADC Captured Data Display Pane
        3. 3.7.1.3 FFT Power Spectrum
        4. 3.7.1.4 Overlay Unwrap Waveform
        5. 3.7.1.5 Single Tone FFT Statistics
      2. 3.7.2 Multi Channel Display
      3. 3.7.3 Unit Selection
      4. 3.7.4 Time Domain
      5. 3.7.5 Two Tone
      6. 3.7.6 Channel Power
    8. 3.8 DAC Display Panel (DAC Mode only)
      1. 3.8.1 Send Button (DAC Mode Only)
      2. 3.8.2 Load File to Transfer into TSW14xxx Button
      3. 3.8.3 Parameter Controls
    9. 3.9 I/Q Multi-Tone Generator
  7. 4 ADC Data Capture Software Operation
    1. 4.1 Testing a TSW1400 EVM with an ADS5281 EVM
    2. 4.2 Testing a TSW1400EVM with an ADS62P49EVM (CMOS Interface)
  8. 5 TSW1400 Pattern Generator Operation
    1. 5.1 Testing a TSW1400 EVM with a DAC3152 EVM
    2. 5.2 Loading DAC Firmware
    3. 5.3 Configuring TSW1400 for Pattern Generation
    4. 5.4 Testing a TSW1400 EVM with a DAC5688EVM (CMOS Interface)
  9. 6 TSW14J58 Functional Description
    1. 6.1 Testing the TSW14J58 EVM with an ADC12DJ3200 EVM
  10. 7 TSW14J57 Functional Description
    1. 7.1 Testing the TSW14J57 EVM with an ADC34J45 EVM
  11. 8 TSW14J56 Functional Description
    1. 8.1 Testing the TSW14J56 EVM with an ADC34J45 EVM
  12. 9 TSW14J50 Functional Description
    1. 9.1 Device Selection
  13. 10TSW14J10 Functional Description
    1. 10.1 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform
    2. 10.2 DAC38J84EVM GUI Setup Example
  14.   A Signal Processing in High Speed Data Converter Pro
    1.     A.1 Introduction
    2.     A.2 FFT Calculation from Time Domain Data
      1.      A.2.1 FFT Window Correction Factor
    3.     A.3 FFT Filtering
    4.     A.4 Single Tone Parameters
      1.      A.4.1 Number of Neighboring Bins for each FFT Window
    5.     A.5 Fundamental Power
      1.      A.5.1 Harmonic Distortions
      2.      A.5.2 SNR
      3.      A.5.3 SFDR
      4.      A.5.4 THD
      5.      A.5.5 SINAD
      6.      A.5.6 ENOB
      7.      A.5.7 Next Spur
    6.     A.6 Two Tone Parameters
    7.     A.7 Average FFT Calculation
    8.     A.8 NSD Calculation
  15.   B History Notes
  16.   C Revision History

10.2 DAC38J84EVM GUI Setup Example

The following example shows what must be modified in the DAC3XJ8X GUI for a setup using 4 lanes, 1x interpolation, and a DAC sample rate of 368.64M.

After opening the DAC GUI, enter the parameters as shown in Figure 10-2.

GUID-CAADCD1F-F38C-4328-988E-B99EFCD4A6E9-low.gif Figure 10-2 Quick Start Menu

The GUI calculates the lane rate and displays it in the box called SerDes Linerate. For this example, the lane rate is 7372.8Mbps. Using the lane rate conditions in Section 10.1, REFCLK = 368.64 MHz and Core clock = 184.32 MHz.

Click on the Program LMK04828 and DAC3XJ8X button. After the programming has completed, click on the LMK04828 Controls tab. Next click on the Clock Outputs tab.

For the DAC3XJ8X GUI, the REFCLK is provided by CLKout 0 and the Core clock is provided by CLKout 12. Notice that the default setting for CLKout 12 is Group Powerdown, as shown in Figure 10-3.

GUID-CA05A94F-5A95-4BF9-BFC7-AF5F52CADDD2-low.gifFigure 10-3 LMK04828 Clock Outputs Menu

Since the DAC Clock is 368.64 MHz, to provide a REFCLK of 368.64 MHz, change the DCLK Divider for CLKout 0 to “8”.

To generate a Core clock of 184.32 MHz, set the DCLK Divider for CLKout 12 to “16”. Also, remove the checkmark from the Group Powerdown box to enable this output. The Clock Outputs menu is now as seen in Figure 10-4.

GUID-047F585C-0EE6-405A-90B8-9D73A5565CFE-low.gifFigure 10-4 LMK04828 Clock Outputs Menu

Open HSDC Pro GUI, select the DAC tab, then select DAC3XJ84_LMF_442 in the device button. After the firmware is loaded, enter 368.64M in the Data Rate (SPS) window, select 2’s Complement in the DAC Option window and generate a 10-MHz test tone using the IQ Multitone Generator located in the lower left of the GUI. Click on the Create Tones button. The display looks as shown in Figure 10-5.

GUID-AC23CDCF-EF69-43CA-8D9F-58B85FF1014D-low.gifFigure 10-5 HSDC Pro GUI

Click the Send button. A new window opens showing the lane rate of the interface and the required frequency of REFCLK, as shown in Figure 10-6.

GUID-09F8E3AE-C95E-4643-995A-57FD7846998E-low.pngFigure 10-6 HSDC Pro GUI: Lane Rate and REFCLK Settings

Go back to the DAC GUI Quick Start tab and click on Reset DAC JESD Core. Click on Trigger LMK04828 SYSREF. There should now be a 10-MHz tone present at all four DAC EVM outputs.