SPRUJ86A October   2023  – January 2024 AM263P4

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 HSEC 180-pin Control Card Docking Station
      2. 1.3.2 Security
  6. 2Hardware
    1. 2.1  Component Identification
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Status LEDs
      3. 2.2.3 Power Tree
      4. 2.2.4 Power Sequence
      5. 2.2.5 PMIC
    3. 2.3  Functional Block Diagram
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Boot Mode Selection
    7. 2.7  JTAG Path Selection
    8. 2.8  Header Information
    9. 2.9  GPIO Mapping
    10. 2.10 Push Buttons
    11. 2.11 Interfaces
      1. 2.11.1  Memory Interface
        1. 2.11.1.1 OSPI/QSPI
        2. 2.11.1.2 Board ID EEPROM
      2. 2.11.2  Ethernet Interface
        1. 2.11.2.1 Control Card Ethernet Routing
        2. 2.11.2.2 On Board Ethernet PHY
        3. 2.11.2.3 LED Indication in RJ45 Connector
      3. 2.11.3  I2C
      4. 2.11.4  Industrial Application LEDs
      5. 2.11.5  SPI
      6. 2.11.6  UART
      7. 2.11.7  MCAN
      8. 2.11.8  FSI
      9. 2.11.9  JTAG
      10. 2.11.10 Test Automation Header
      11. 2.11.11 LIN
      12. 2.11.12 MMC
      13. 2.11.13 ADC and DAC
    12. 2.12 HSEC Pinout and Pinmux Mapping
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 If You Need Assistance
    2. 4.2 Trademarks
  9. 5Related Documentation
    1. 5.1 Supplemental Content
      1.      5.1.A E1 Board Modifications
      2.      5.1.B E2 Design Changes
  10. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  11. 7Revision History

2.11.2.2 On Board Ethernet PHY

The AM263Px Control Card uses one port of RGMII signals and the PRU0 core of the PRU-ICSS to be connected to a 48pin ethernet PHY (DP83TG730SWRHARQ1). The PHY is configured to advertise 1-Gb operation. The ethernet data signals of the PHY are terminated to an RJ45 Connector. LEDs are used to indicate link status and activity.

GUID-5A832195-1D18-4E06-992E-CCC0474F9AAC-low.png Figure 2-21 E1 Control Card On Board Ethernet PHY

The Ethernet PHY requires three separate power sources. There are two dedicated LDO for the 1.1 V and 2.5 V supplies for the Ethernet PHY. The VDDIO supply for the ethernet PHY is supplied through a load switch (U16) that is enabled once the 2.5 V power good signal is driven high.

The RGMII2 port of the CPSW signals are internally muxed on the same balls as the PRU-ICSS ethernet signals. To use RGMII2, the balls must be set to the appropriate mux mode for RGMII2.

There are series termination resistors on the transmit and receive clock signals located near the AM263Px SoC.

The MDIO and Interrupt signals from the SoC to the PHY require 2.2KΩ pull up resistors to the I/O supply voltage for proper operation. The interrupt signal is driven by a GPIO signal that is mapped from the AM263Px SoC.

The reset signal for the Ethernet PHY is driven by a 2-input AND gate. The AND gate's inputs are a GPIO signal that is generated by the IO Expander and PORz.

The Ethernet PHY uses many functional pins as strap option to place the device into specific modes of operation.

GUID-1D9E5424-C3EB-418E-9C00-D9CA1726C19B-low.png Figure 2-22 Industrial Ethernet PHY Strapping Resistors
Table 2-17 Industrial Gigabit Ethernet PHY Strapping Resistors
Functional Pin Default Mode Mode in CC Function
RX_D0 0 0 PHY address: 0000
RX_D1 0 0
JTAG_TDO/GPIO_1 0 0 RGMII to Copper
RX_D3 0 0
RX_D2 0 0
LED_0 0 0 Auto-negotiation, 1000/100/10 advertised, auto MDI-X
RX_ER 0 0
LED_2 0 0
RX_DV 0 0 Port Mirroring Disabled