SPRUJ86A October   2023  – January 2024 AM263P4

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 HSEC 180-pin Control Card Docking Station
      2. 1.3.2 Security
  6. 2Hardware
    1. 2.1  Component Identification
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Status LEDs
      3. 2.2.3 Power Tree
      4. 2.2.4 Power Sequence
      5. 2.2.5 PMIC
    3. 2.3  Functional Block Diagram
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Boot Mode Selection
    7. 2.7  JTAG Path Selection
    8. 2.8  Header Information
    9. 2.9  GPIO Mapping
    10. 2.10 Push Buttons
    11. 2.11 Interfaces
      1. 2.11.1  Memory Interface
        1. 2.11.1.1 OSPI/QSPI
        2. 2.11.1.2 Board ID EEPROM
      2. 2.11.2  Ethernet Interface
        1. 2.11.2.1 Control Card Ethernet Routing
        2. 2.11.2.2 On Board Ethernet PHY
        3. 2.11.2.3 LED Indication in RJ45 Connector
      3. 2.11.3  I2C
      4. 2.11.4  Industrial Application LEDs
      5. 2.11.5  SPI
      6. 2.11.6  UART
      7. 2.11.7  MCAN
      8. 2.11.8  FSI
      9. 2.11.9  JTAG
      10. 2.11.10 Test Automation Header
      11. 2.11.11 LIN
      12. 2.11.12 MMC
      13. 2.11.13 ADC and DAC
    12. 2.12 HSEC Pinout and Pinmux Mapping
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 If You Need Assistance
    2. 4.2 Trademarks
  9. 5Related Documentation
    1. 5.1 Supplemental Content
      1.      5.1.A E1 Board Modifications
      2.      5.1.B E2 Design Changes
  10. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  11. 7Revision History

2.8 Header Information

This version of the AM263Px has 11 different headers. For the locations of each header, refer to Section 2.1. The signal details for each header pin is detailed below.

  • PMIC Headers
    • For more information about the PMIC, refer to Table 3-6.
Table 2-6 PMIC
Designator Pin 1 Pin 2 Pin 3
J2 VCC_PLDO2 NC DGND
J3 VCC_PLDO1 NC DGND
J20 VMAIN_12V0 PMIC_WKUP1 N/A
J21 TCAN_WAKE DGND N/A
  • Test Automation Bootmode Control Header
    • For more information about the Test Automation Header, refer to Table 3-7.
Table 2-7 Test Automation Header
Designator Pin 1 Pin 2
J12 TA_GPIO3 DGND
  • MCAN Header
    • For more information about the MCAN interface, refer to Table 3-8.
Table 2-8 MCAN Header
Designator Pin 1 Pin 2 Pin 3
J5 MCAN4_CAN_H DGND MCAN4_CAN_L
J21 TCAN_WAKE DGND N/A
J22 PMIC_WKUP2 MCAN INH N/A
  • FSI Header
    • For more information about the FSI Interface, refer to Table 3-9.
Table 2-9 FSI Header
Designator Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10
J6 FSIRX2_CLK FSITX2_CLK DGND DGND FSIRX2_DATA0 FSITX2_DATA0 FSIRX2_DATA1 FSITX2_DATA1 DGND VSYS_3V3A
  • PRU-ICSS IEP Headers
    • For more information about the PRU-ICSS, refer to Table 3-10.
Table 2-10 PRU-ICSS IEP Headers
Designator Pin 1 Pin 2
J19 PR0_IEP0_EDIO_DATA_IN_OUT_31 DGND
J18 PR0_IEP0_EDC_SYNC_OUT1 DGND
J17 PR0_IEP0_EDIO_DATA_IN_OUT_30 DGND
J16 PR0_IEP0_EDC_SYNC_OUT0 DGND
  • LIN Headers
    • For more information about the LIN interface, refer to Table 3-11.
Table 2-11 LIN Headers
Designator Pin 1 Pin 2 Pin 3
J10 VLIN LIN DGND
J9 VBAT_LIN DGND N/A