SPRUJB5 February   2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 Specification
  8. 2Hardware
    1. 2.1 Key Features and Interfaces
    2. 2.2 Power On/Off Procedure
    3. 2.3 Power Input
      1. 2.3.1 Power Input
      2. 2.3.2 Power Budget Considerations
    4. 2.4 User Inputs and Settings
      1. 2.4.1 Boot Configuration Settings
      2. 2.4.2 Board Configuration Settings
      3. 2.4.3 Reset Pushbutton
      4. 2.4.4 User Pushbutton And LEDs
    5. 2.5 Standard Interfaces
      1. 2.5.1 Audio Input/Output
      2. 2.5.2 DisplayPort and HDMI
      3. 2.5.3 Gigabit Ethernet
      4. 2.5.4 JTAG and Emulation
      5. 2.5.5 MicroSD Card Cage
      6. 2.5.6 PCIe Card Module
      7. 2.5.7 UARTs for Terminal and Logging
      8. 2.5.8 USB Interfaces
    6. 2.6 Expansion Interfaces
      1. 2.6.1 Camera Interface, 22-Pin Flex
      2. 2.6.2 Camera Interface, 40-Pin Expansion
      3. 2.6.3 CAN-Bus Interface
      4. 2.6.4 DSI Display Interface
      5. 2.6.5 OLDI/LVDS Display Interface
      6. 2.6.6 User Expansion Header
    7. 2.7 Circuit Details
      1. 2.7.1 Interface Mapping
      2. 2.7.2 I2C Address Mapping
      3. 2.7.3 GPIO Mapping
      4. 2.7.4 I2C GPIO Expander Mapping
      5. 2.7.5 Power Monitoring
      6. 2.7.6 Identification EEPROM
      7. 2.7.7 Memory and Storage
      8. 2.7.8 Power Distribution
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Compliance Information
    1. 4.1 Thermal Compliance
    2. 4.2 EMC, EMI, and ESD Compliance
  11. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

2.7.8 Power Distribution

The EVM utilizes an array of DC-DC converters and linear regulators to power the processor, memories, and peripheral components with the necessary voltage and power required. The figure below shows the high level power architecture used on the EVM.

GUID-20240214-SS0I-J3TB-KZNW-N1VTB5PCR70V-low.jpg Figure 2-5 Power Architecture

The power flow begins from an external supply connecting to the USB Type-C power connector [J24]. See Section 2.3 for specifics on external power supply requirements. The USB Power Delivery device (TPS25750D) negotiates the input voltage from 5V up to 20V depending upon input supply capability. The 1st Stage Power regulators then generate the EVMs primary power rails of 3.3Volts (LM5141-Q1), 5.0Volts (LM61480-Q1), and 12.0Volts (LM5141-Q1). A small 3.3Volt regulator (TPS62177) is used for management circuitry to control EVM ON/OFF features with push-buttons. Some of the on-board peripherals of the EVM have specific voltage and power requirements and are satisfied with several linear regulators (TPS74801-Q1).

The Power Management IC (TPS6522311-Q1) is specifically designed to meet the voltage, power, and sequencing requirements of the processor. The PMIC includes the capability to manage supplemental regulators and is capable of meeting ASIL-B safety requirements. The low voltage, high current power rail of the processor is sourced from a stackable SMSP regulator (TPS62875-Q1) to allow for power design size optimization based on the specific applications power needs. This specific PDN implementation includes additional power resources to support advance low power modes such as IO and DDR Retention. Additional power resources are also included to provide the ability to demonstrate both high performance use-cases (operating at 0.85V) and the lower power or performance use cases (operating at 0.75V).