LMK03328
- Ultra Low Noise, High Performance
- Jitter: 100-fs RMS Typical, FOUT > 100 MHz
- PSNR: –80 dBc, Robust Supply Noise Immunity
- Flexible Device Options
- Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or Any Combination
- Pin Mode, I2C Mode, and EEPROM Mode
- 71-Pin Selectable Pre-Programmed Default Start-Up Options
- Dual Inputs With Automatic or Manual Selection
- Crystal Input: 10 to 52 MHz
- External Input: 1 to 300 MHz
- Frequency Margining Options
- Fine Frequency Margining (±50 ppm Typical) Using Low-Cost Pullable Crystal Reference
- Glitchless Coarse Frequency Margining (%) Using Output Dividers
- Other Features
- Supply: 3.3-V Core, 1.8-V, 2.5-V, 3.3-V Output Supply
- Industrial Temperature Range (–40ºC to +85ºC)
- Package: 7-mm × 7-mm 48-WQFN
The LMK03328 device is an ultra-low-noise clock generator with two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution and fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, reduces BOM cost and board area, and improves reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.
For each PLL, a differential/single-ended clock or crystal input can be selected as the PLL reference clock. The selected PLL reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input frequency. The VCO frequency for the respective PLLs can be tuned between 4.8 GHz and 5.4 GHz. Both PLL/VCOs are equivalent in performance and functionality. Each PLL offers the flexibility to select a predefined or user-defined loop bandwidth, depending on the needs of the application. Each PLL has a post-divider that can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.
All the output channels can select the divided-down VCO clock from PLL1 or PLL2 as the source for the output divider to set the final output frequency. Some output channels can also independently select the reference input for PLL1 or PLL2 as an alternative source to be bypassed to the corresponding output buffers. The 8-bit output dividers support a divide range of 1 to 256 (even or odd), output frequencies up to 1 GHz, and output phase synchronization capability.
All output pairs are ground-referenced CML drivers with programmable swing that can be interfaced to LVDS or LVPECL or CML receivers with AC coupling. All output pairs can also be independently configured as HCSL outputs or 2x 1.8-V LVCMOS outputs. The outputs offer lower power at 1.8 V, higher performance and power supply noise immunity, and lower EMI compared to voltage-referenced driver designs (such as traditional LVDS and LVPECL drivers). Two additional 3.3-V LVCMOS outputs can be obtained through the STATUS pins. This is an optional feature in case of a need for 3.3-V LVCMOS outputs and device status signals are not needed.
The device features self start-up from on-chip programmable EEPROM or pre-defined ROM memory, which offers multiple custom device modes selectable through pin control and can eliminate the need for serial programming. The device registers and on-chip EEPROM settings are fully programmable via I2C-compatible serial interface. The device slave address is programmable in EEPROM and LSBs are settable with a 3-state pin.
The device provides two frequency margining options with glitch-free operation to support system design verification tests (DVT), such as standard compliance and system timing margin testing. Fine frequency margining (in ppm) can be supported by using a low-cost pullable crystal on the internal crystal oscillator (XO), and selecting this input as the reference to the PLL synthesizer. The frequency margining range is determined by the crystal’s trim sensitivity and the on-chip varactor range. XO frequency margining can be controlled through pin or I2C control for ease-of-use and high flexibility. Coarse frequency margining (in %) is available on any output channel by changing the output divide value through I2C interface, which synchronously stops and restarts the output clock to prevent a glitch or runt pulse when the divider is changed.
Internal power conditioning provide excellent power supply noise rejection (PSNR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from 3.3-V ± 5% supply and output blocks operate from 1.8-V, 2.5-V, 3.3-V ± 5% supply.
관심 가지실만한 유사 제품
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
기술 문서
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
LMK03328EVM — LMK03328EVM 초저지터 클록 제너레이터 EVM(PLL 2개, 차동 출력 8개, 입력 2개 지원)
LMK03328EVM 평가 모듈은 듀얼 PLL, 8개 출력, 2개 입력 및 통합 EEPROM을 갖춘 텍사스 인스트루먼트 LMK03328 초저지터 클록 생성기의 100fs RMS 지터 성능 및 핀/소프트웨어 구성 모드 및 기능을 평가할 수 있는 완전한 클로킹 플랫폼을 제공합니다.
LMK03328EVM은 규정 준수 테스트, 성능 평가 및 초기 시스템 프로토타이핑을 위한 유연한 멀티 출력 클록 소스로 사용할 수 있습니다. 에지-런치 SMA 포트는 상업적으로 사용 가능한 동축 케이블, 어댑터 또는 발룬(미포함)을 사용하여 장비 및 레퍼런스 (...)
TICSPRO-SW — TICS Pro v1.7.7.2, 05-Feb-2024
Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
지원되는 제품 및 하드웨어
제품
클록 생성기
RF PLL 및 신시사이저
클록 지터 클리너 및 싱크로나이저
클록 버퍼
오실레이터
하드웨어 개발
평가 보드
소프트웨어
IDE, 구성, 컴파일러 또는 디버거
CLOCK-TREE-ARCHITECT — 클록 트리 아키텍트 프로그래밍 소프트웨어
PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
지원되는 제품 및 하드웨어
제품
RF PLL 및 신시사이저
클록 지터 클리너 및 싱크로나이저
클록 버퍼
클록 생성기
IQ 복조기
하드웨어 개발
평가 보드
소프트웨어
애플리케이션 소프트웨어 및 프레임워크
IDE, 구성, 컴파일러 또는 디버거
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
패키지 | 핀 | 다운로드 |
---|---|---|
WQFN (RHS) | 48 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.