UCC27524A-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results
- Device Temperature Grade 1
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C4B
- Industry-Standard Pin Out
- Two Independent Gate-Drive Channels
- 5-A Peak Source and Sink-Drive Current
- Independent Enable Function for Each Output
- TTL and CMOS-Compatible Logic Threshold
Independent of Supply Voltage - Hysteretic-Logic Thresholds for High-Noise
Immunity - Ability to Handle Negative Voltages (–5 V) at
Inputs - Inputs and Enable Pin-Voltage Levels Not
Restricted by VDD Pin Bias Supply Voltage - 4.5-V to 18-V Single-Supply Range
- Outputs Held Low During VDD-UVLO, (ensures
glitch-free operation at power-up and power-
down) - Fast Propagation Delays (13-ns typical)
- Fast Rise and Fall Times (7-ns and 6-ns typical)
- 1-ns Typical Delay Matching Between 2-Channels
- Ability to Parallel Two Outputs for High-Drive
Current - Outputs Held in LOW When Inputs are Floating
- SOIC-8 and MSOP-8 PowerPad™ Package Options
- Operating Temperature Range of –40°C to 140°C
The UCC27524A-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A-Q1 device is a variant of the UCC2752x family. The UCC27524A-Q1 device adds the ability to handle 5 V directly at the input pins for increased robustness. The UCC27524A-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A-Q1 device is capable of delivering high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 13 ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.
For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.
The UCC27524A-Q1 devices is available in SOIC-8 (D) and MSOP-PowerPAD-8 with exposed pad (DGN) packages.
관심 가지실만한 유사 제품
비교 대상 장치보다 업그레이드된 기능을 지원하는 즉각적 대체품
기술 문서
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | UCC27524A-Q1 Dual 5-A, High-Speed, Low-Side Gate Driver With Negative Input Voltage Capability datasheet (Rev. B) | PDF | HTML | 2015/07/24 |
Application note | Why use a Gate Drive Transformer? | PDF | HTML | 2024/03/04 | |
Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020/02/28 | ||
Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020/02/28 | ||
More literature | Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) | 2018/10/29 | ||
White paper | Driving the future of HEV/EV with high-voltage solutions (Rev. B) | 2018/05/16 | ||
Technical article | Are you on-board? Demystifying EV charging systems | PDF | HTML | 2017/07/31 |
설계 및 개발
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패키지 | 핀 | 다운로드 |
---|---|---|
HVSSOP (DGN) | 8 | 옵션 보기 |
SOIC (D) | 8 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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