SBAS978A June 2019 – May 2020 ADS7028
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The variation in ADC offset error resulting from changes in temperature or AVDD can be calibrated by setting the CAL bit in the GENERAL_CFG register. The CAL bit is reset to 0 after calibration. The host can poll the CAL bit to check the ADC offset calibration completion status.