8.5.108 GPO3_TRIG_EVENT_SEL Register (Address = 0xC9) [reset = 0x4]
GPO3_TRIG_EVENT_SEL is shown in Figure 146 and described in Table 118.
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Figure 146. GPO3_TRIG_EVENT_SEL Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
GPO3_TRIG_EVENT_SEL[7:0] |
R/W-100b |
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Table 118. GPO3_TRIG_EVENT_SEL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-0 |
GPO3_TRIG_EVENT_SEL[7:0] |
R/W |
100b |
Select the inputs AIN/GPIO[7:0] which can trigger an event based update on GPO3.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO3 output.
1b = Alert flags for the AIN/GPIO corresponding to this bit trigger GPO3 output.
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