SPRSPA3A March 2024 – September 2024 AM67 , AM67A
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
SIGNAL NAME [1] | PIN TYPE [2] | DESCRIPTION [3] | AMW PIN [4] |
---|---|---|---|
DDR0_CAS_n (1) | O | DDRSS Column Address Strobe / LPDDR4 Chip Select 1B | M4 |
DDR0_RAS_n (1) | O | DDRSS Row Address Strobe / LPDDR4 Chip Select 0B | M3 |
DDR0_A0 | O | DDRSS Address Bus | L4 |
DDR0_A1 | O | DDRSS Address Bus | L6 |
DDR0_A2 | O | DDRSS Address Bus | M5 |
DDR0_A3 | O | DDRSS Address Bus | L3 |
DDR0_A4 | O | DDRSS Address Bus | N2 |
DDR0_A5 | O | DDRSS Address Bus | L2 |
DDR0_CAL0 (2) | A | IO Pad Calibration Resistor | R6 |
DDR0_CK0 | O | DDRSS Clock | P1 |
DDR0_CK0_n | O | DDRSS Negative Clock | N1 |
DDR0_CKE0 | O | DDRSS Clock Enable | P2 |
DDR0_CKE1 | O | DDRSS Clock Enable | P6 |
DDR0_CS0_n (1) | O | DDRSS Chip Select 0 / LPDDR4 Chip Select 0A | P4 |
DDR0_CS1_n (1) | O | DDRSS Chip Select 1 / LPDDR4 Chip Select 1A | P3 |
DDR0_DM0 | IO | DDRSS Data Mask | G2 |
DDR0_DM1 | IO | DDRSS Data Mask | H6 |
DDR0_DM2 | IO | DDRSS Data Mask | U4 |
DDR0_DM3 | IO | DDRSS Data Mask | AA2 |
DDR0_DQ0 | IO | DDRSS Data | D6 |
DDR0_DQ1 | IO | DDRSS Data | D2 |
DDR0_DQ2 | IO | DDRSS Data | F6 |
DDR0_DQ3 | IO | DDRSS Data | D3 |
DDR0_DQ4 | IO | DDRSS Data | G4 |
DDR0_DQ5 | IO | DDRSS Data | E2 |
DDR0_DQ6 | IO | DDRSS Data | G6 |
DDR0_DQ7 | IO | DDRSS Data | F3 |
DDR0_DQ8 | IO | DDRSS Data | H5 |
DDR0_DQ9 | IO | DDRSS Data | H2 |
DDR0_DQ10 | IO | DDRSS Data | K2 |
DDR0_DQ11 | IO | DDRSS Data | L1 |
DDR0_DQ12 | IO | DDRSS Data | J6 |
DDR0_DQ13 | IO | DDRSS Data | J4 |
DDR0_DQ14 | IO | DDRSS Data | J2 |
DDR0_DQ15 | IO | DDRSS Data | H3 |
DDR0_DQ16 | IO | DDRSS Data | V3 |
DDR0_DQ17 | IO | DDRSS Data | R2 |
DDR0_DQ18 | IO | DDRSS Data | R5 |
DDR0_DQ19 | IO | DDRSS Data | T2 |
DDR0_DQ20 | IO | DDRSS Data | R3 |
DDR0_DQ21 | IO | DDRSS Data | U2 |
DDR0_DQ22 | IO | DDRSS Data | U5 |
DDR0_DQ23 | IO | DDRSS Data | V2 |
DDR0_DQ24 | IO | DDRSS Data | Y2 |
DDR0_DQ25 | IO | DDRSS Data | W4 |
DDR0_DQ26 | IO | DDRSS Data | V5 |
DDR0_DQ27 | IO | DDRSS Data | W2 |
DDR0_DQ28 | IO | DDRSS Data | V6 |
DDR0_DQ29 | IO | DDRSS Data | W3 |
DDR0_DQ30 | IO | DDRSS Data | AA3 |
DDR0_DQ31 | IO | DDRSS Data | AA5 |
DDR0_DQS0 | IO | DDRSS Data Strobe | E1 |
DDR0_DQS0_n | IO | DDRSS Complimentary Data Strobe | F1 |
DDR0_DQS1 | IO | DDRSS Data Strobe | H1 |
DDR0_DQS1_n | IO | DDRSS Complimentary Data Strobe | J1 |
DDR0_DQS2 | IO | DDRSS Data Strobe | T1 |
DDR0_DQS2_n | IO | DDRSS Complimentary Data Strobe | U1 |
DDR0_DQS3 | IO | DDRSS Data Strobe | W1 |
DDR0_DQS3_n | IO | DDRSS Complimentary Data Strobe | Y1 |
DDR0_RESET0_n | O | DDRSS Reset | U6 |