6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER			MIN	MAX	UNIT
VDD_CORE	Core supply		-0.3	1.05	V
VDDR_CORE	RAM core supply		-0.3	1.05	V
VDD_CANUART	CANUART core supply		-0.3	1.05	V
VDDA_CORE_CSI_DSI	CSIRX0 and DSITX0 core supply		-0.3	1.05	V
VDDA_CORE_CSI_DSI_CLK	CSIRX0 and DSITX0 clock core supply		-0.3	1.05	V
VDDA_CORE_USB0 VDDA_CORE_USB1	USB0 and USB1 core supply		-0.3	1.05	V
VDDA_DDR_PLL0	DDR deskew PLL supply		-0.3	1.05	V
VDD_MMC0	MMC0 PHY core supply		-0.3	1.05	V
VDDA_0P85_DLL_MMC0	MMC0 DLL analog supply		-0.3	1.05	V
VDDA_0P85_SERDES VDDA_0P85_SERDES_C	SERDES analog supply		-0.3	1.05	V
VDDS_DDR	DDR PHY IO supply		-0.3	1.57	V
VDDS_DDR_C	DDR clock IO supply		-0.3	1.57	V
VDDA_1P8_SERDES	SERDES PHY IO supply		-0.3	1.98	V
VDDS_MMC0	MMC0 PHY IO supply		-0.3	1.98	V
VDDS_OSC0	MCU_OSC0 and WKUP_LFOSC0 supply		-0.3	1.98	V
VDDA_MCU	RCOSC, POR, POK, and MCU PLL analog supply		-0.3	1.98	V
VDDA_PLL0	SMS PLL analog supply		-0.3	1.98	V
VDDA_PLL1	MAIN PLL, PER0 PLL, and PER1 PLL analog supply		-0.3	1.98	V
VDDA_PLL2	DDR PLL and ARM0 PLL analog supply		-0.3	1.98	V
VDDA_PLL3	VIDEO PLL and GPU PLL analog supply		-0.3	1.98	V
VDDA_PLL4	DSS PLL0, DSS PLL1, and DSS PLL2 analog supply		-0.3	1.98	V
VDDA_PLL5	C7x PLL analog supply		-0.3	1.98	V
VDDA_1P8_CSI_DSI	CSIRX0 and DSITX0 1.8 V analog supply		-0.3	1.98	V
VDDA_1P8_OLDI0	OLDI0 1.8 V analog supply		-0.3	1.98	V
VDDA_1P8_USB0 VDDA_1P8_USB1	USB0 and USB1 1.8 V analog supply		-0.3	1.98	V
VDDA_TEMP0	TEMP0 analog supply		-0.3	1.98	V
VDDA_TEMP1	TEMP1 analog supply		-0.3	1.98	V
VDDA_TEMP2	TEMP2 analog supply		-0.3	1.98	V
VPP	eFuse ROM programming supply		-0.3	1.98	V
VDDSHV_MCU	IO supply for IO group MCU		-0.3	3.63	V
VDDSHV_CANUART	IO supply for IO group CANUART		-0.3	3.63	V
VDDSHV0	IO supply for IO group 0		-0.3	3.63	V
VDDSHV1	IO supply for IO group 1		-0.3	3.63	V
VDDSHV2	IO supply for IO group 2		-0.3	3.63	V
VDDSHV3	IO supply for IO group 3		-0.3	3.63	V
VDDSHV5	IO supply for IO group 5		-0.3	3.63	V
VDDSHV6	IO supply for IO group 6		-0.3	3.63	V
VDDA_3P3_USB0 VDDA_3P3_USB1	USB0 and USB1 3.3 V analog supply		-0.3	3.63	V
Steady-state max voltage at all fail-safe IO pins		MCU_PORz	-0.3	3.63	V
		MCU_I2C0_SCL, MCU_I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA, EXTINTn When operating at 1.8V	-0.3	1.98⁽³⁾	V
		MCU_I2C0_SCL, MCU_I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA, EXTINTn When operating at 3.3V	-0.3	3.63⁽³⁾
		VMON_1P8_SOC	-0.3	1.98	V
		VMON_3P3_SOC	-0.3	3.63	V
		VMON_VSYS⁽⁴⁾	-0.3	1.98	V
Steady-state max voltage at all other IO pins⁽⁵⁾		USB0_VBUS, USB1_VBUS⁽⁶⁾	-0.3	3.6	V
Steady-state max voltage at all other IO pins⁽⁵⁾		All other IO pins	-0.3	IO supply voltage + 0.3	V
Transient overshoot and undershoot at IO pin		20% of IO supply voltage for up to 20% of the signal period (see Figure 6-1)		0.2 × VDD⁽⁷⁾	V
Latch-up performance⁽⁸⁾		I-Test	-100	100	mA
Latch-up performance⁽⁸⁾		Over-Voltage (OV) Test		1.5 x VDD⁽⁷⁾	V
T_STG	Storage temperature		-55	+150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to VSS, unless otherwise noted.

(3) The absolute maximum ratings for these fail-safe pins depends on their IO supply operating voltage. Therefore, this value is also defined by the maximum V_IH value found in the I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics section, where the electrical characteristics table has separate parameter values for 1.8-V mode and 3.3-V mode.

(4) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see System Power Supply Monitor Design Guidelines.

(5) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be –0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences.

(6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see the USB VBUS Design Guidelines.

(7) VDD is the voltage on the corresponding power-supply pin(s) for the IO.

(8) For current pulse injection (I-Test):

Pins stressed per JEDEC JESD78 (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.

For over-voltage performance (Over-Voltage (OV) Test):

Supplies stressed per JEDEC JESD78 (Class II) and passed specified voltage injection.

Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off. The MCU_I2C0_SCL, MCU_I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA, EXTINTn, VMON_1P8_SOC, VMON_3P3_SOC, and MCU_PORz are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 6.1.

A. T_overshoot + T_undershoot < 20% of T_period

Figure 6-1 IO Transient Voltage Ranges